
Mitsubishi microcomputers
M16C / 62 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory Space Expansion Functions
24
(3) Expansion mode 2
In expansion mode 2, the data bank register (0000B
16
) goes effective. Figure 1.8.4 shows the data bank
register.
Figure 1.8.4. Data bank register
Data bank register
Symbol
DBR
Address
000B
16
When reset
00
16
Bit name
Description
Bit symbol
W
R
b7
b6
b5
b4
b3
b2
b1
b0
OFS
Offset bit
0: Not offset
1: Offset
BSR
Bank selection bits
0 1 0: Bank 2
1 0 0: Bank 4
1 1 0: Bank 6
0 1 1: Bank 3
1 0 1: Bank 5
1 1 1: Bank 7
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
b5 b4 b3
b5 b4 b3
Microprocessor
mode
AAAA
AAAA
SFR area
Internal RAM area
External area
Internal area reserved
00000
16
00400
16
XXXXX
16
YYYYY
16
FFFFF
16
D0000
16
AAAAAAAA
Internal area reserved
08000
AAAAAAAA
28000
16
Memory
expansion mode
40000
16
SFR are
a
Internal RAM area
External area
Internal ROM area
Internal area reserved
CS3
(16K bytes)
CS2
(128K bytes)
CS1
(96K bytes)
04000
16
Expansion mode 2 (memory space = 4M bytes for PM15 = 1, PM14 = 1)
CS0
Addresses from 40000
16
through BFFFF
16
Bank 7 in fetching a program
A bank selected by use of the bank selection
bits in accessing data
Addresses from C0000
16
through FFFFF
16
Bank 7 invariably
Bank number is output to CS3 to CS1
Note 1: These memory maps show an instance in which PM13 is set to 0; but in the case of M30624MG/FG, they
show an instance in which PM13 is set to 1.
Note 2: The memory maps in single-chip mode are omitted.
Memory expansion mode:
512K bytes x 7banks +
256K bytes
Microprocessor mode:
512K bytes x 8banks
M30622M4
M30620M8
M30620MA
M30620MC/EC
00FFF
16
02BFF
16
02BFF
16
02BFF
16
F8000
16
F0000
16
E8000
16
E0000
16
C0000
16
053FF
16
M30624MG/FG
E8000
16
E0000
16
017FF
16
017FF
16
M30622MA
M30622MC
M30622M8/E8
F0000
16
013FF
16
Address XXXXX
16
Type No.
Address YYYYY
16
Figure 1.8.5. Memory location and chip select area in expansion mode 2