參數(shù)資料
型號(hào): M30622MGP-XXXFP
元件分類(lèi): 微控制器/微處理器
英文描述: 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù): 64/104頁(yè)
文件大?。?/td> 1313K
代理商: M30622MGP-XXXFP
5. Electrical Characteristics
Rev.2.41
Jan 10, 2006
Page 60 of 96
REJ03B0001-0241
Figure 5.7
Timing Diagram (5)
BCLK
CSi
td(BCLK-CS)
25ns.max
ADi
td(BCLK-AD)
25ns.max
ALE
25ns.max
th(BCLK-ALE)
-4ns.min
RD
25ns.max
th(BCLK-RD)
0ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
Hi-Z
DBi
tsu(DB-RD)
40ns.min
th(RD-DB)
0ns.min
tcyc
BHE
Read timing
WR, WRL,
WRH
25ns.max
th(BCLK-WR)
0ns.min
BCLK
CSi
td(BCLK-CS)
25ns.max
ADi
td(BCLK-AD)
25ns.max
ALE
25ns.max
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
tcyc
th(WR-AD)
BHE
td(BCLK-DB)
40ns.max
4ns.min
th(BCLK-DB)
td(DB-WR)
(0.5
× tcyc-40)ns.min
(0.5
× tcyc-10)ns.min
th(WR-DB)
DBi
Write timing
td(BCLK-ALE)
td(BCLK-RD)
td(BCLK-WR)
0ns.min
th(RD-AD)
tac2(RD-DB)
Hi-Z
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Measuring conditions
VCC1=VCC2=5V
Input timing voltage : VIL=0.8V, VIH=2.0V
Output timing voltage : VOL=0.4V, VOH=2.4V
(1.5
× tcyc-45)ns.max
tcyc=
f(BCLK)
1
(0.5
× tcyc-10)ns.min
VCC1=VCC2=5V
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