34
Mitsubishi microcomputers
M16C / 62T Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
W
Function
Bit symbol
Bit name
Chip select control register
Symbol
Address
When reset
CSR
000816
0116
R
b7
b6
b5
b4
b3
b2
b1
b0
CS1
CS0
CS3
CS2
CS0 output enable bit
CS1 output enable bit
CS2 output enable bit
CS3 output enable bit
CS1W
CS0W
CS3W
CS2W
CS0 wait bit
CS1 wait bit
CS2 wait bit
CS3 wait bit
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
0 : Wait state inserted
1 : No wait state
Note: In M30623(80-pin package), the chip select signals has no corresponding
external pin. So, this register is invalid.
Figure 1.12.1. Chip select control register
(3) Read/write signals
With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the
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combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE
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pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0
(address 000416) to “0”.) Tables 1.12.2 and 1.12.3 show the operation of these signals.
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After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
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When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 000416) has been set (Note 1).
Note 1: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
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Table 1.12.3. Operation of RD, WR, and BHE signals
Status of external data bus
RD
BHE
WR
HL
L
LHL
HLH
LH
H
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Data bus width
A0
H
L
HL
L
LHL
L
HL
H / L
LH
H / L
8-bit
(BYTE = “H”)
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
16-bit
(BYTE = “L”)
Not used
Status of external data bus
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
WRH
WRL
RD
Data bus width
16-bit
(BYTE = “L”)
H
L
H
L
H
L
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Table 1.12.2. Operation of RD, WRL, and WRH signals
Note 1: M30623(80-pin package) can operate only when BYTE = ‘‘H’’.