參數(shù)資料
型號(hào): M30624MHP-XXXGP
元件分類(lèi): 微控制器/微處理器
英文描述: 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù): 83/104頁(yè)
文件大小: 1313K
代理商: M30624MHP-XXXGP
1. Overview
Page 6 of 96
Figure 1.2
M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram
Timer (16-bit)
Output (timer A): 5
Input (timer B): 6
Internal peripheral functions
Watchdog timer
(15 bits)
DMAC
(2 channels)
D/A converter
(8 bits X 2 channels)
A/D converter
(10 bits X 8 channels
Expandable up to 26 channels)
UART or
clock synchronous serial I/O (2 channels)
UART
(1 channel)
System clock
generation circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
M16C/60 series16-bit CPU core
Port P0
8
Port P2
8
Port P3
8
Port P4
4
Port P5
8
Port P6
8
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
Memory
4
7
8
Po
rt
P
1
0
Po
rt
P
9
Por
tP
8
Por
tP
7
P
o
rt
P8_5
ROM (1)
RAM (2)
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. To use a UART2, set the CRD bit in the U2C0 register to “1” (CTS/RTS function disabled).
4. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.
Clock synchronous serial I/O
(8 bits X 2 channels)
R0L
R0H
R1H
R1L
R2
R3
SB
FLG
USP
ISP
INTB
PC
Multiplier
A0
A1
FB
(4)
(4
)
(3)
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