Serial I/O
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
92
UARTi transmit/receive control register 0
Symbol
Address
When reset
UiC0(i=0,1)
03A416, 03AC16
0816
b7
b6
b5
b4
b3
b2
b1
b0
Function
(During UART mode)
W
R
Function
(During clock synchronous
serial I/O mode)
TXEPT
CLK1
CLK0
CRS
CRD
NCH
CKPOL
BRG count source
select bit
Transmit register
empty flag
CLK polarity
select bit
CTS/RTS function
select bit
CTS/RTS disable
bit
Data output
select bit
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
b1 b0
0 : LSB first
1 : MSB first
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
programmable I/O port)
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
UFORM Transfer format
select bit
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
b1 b0
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
Must always be “0”
Bit name
Bit
symbol
Must always be “0”
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
programmable I/O port)
UART2 transmit/receive control register 0
Symbol
Address
When reset
U2C0
037C16
0816
b7
b6
b5
b4
b3
b2
b1
b0
Function
(During UART mode)
W
R
Function
(During clock synchronous
serial I/O mode)
TXEPT
CLK1
CLK0
CRS
CRD
CKPOL
BRG count source
select bit
Transmit register
empty flag
0 : Transmit data is output at falling
edge of transfer clock and receive
data is input at rising edge
1 : Transmit data is output at rising
edge of transfer clock and receive
data is input at falling edge
CLK polarity
select bit
CTS/RTS function
select bit
CTS/RTS disable
bit
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
b1 b0
0 : LSB first
1 : MSB first
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P73 functions
programmable I/O port)
UFORM Transfer format
select bit (Note 3)
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
b1 b0
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
Must always be “0”
Bit name
Bit
symbol
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Note 4: The setting value of these bits are invalid since CLK2 and CTS2/RTS2 do not have external pin in
M16C/62 (80-pin version) group.
Note 5: UART2 clock synchronous serial I/O mode cannot be used in M16C/62 (80-pin version) group.
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P73 functions programmable
I/O port)
0 : LSB first
1 : MSB first
0 : Transmit data is output at falling
edge of transfer clock and receive
data is input at rising edge
1 : Transmit data is output at rising
edge of transfer clock and receive
data is input at falling edge
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
Figure 1.14.6. Serial I/O-related registers (3)