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| 型號： | M3062AFCTGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 77/104頁 |
| 文件大?。?/td> | 1313K |
| 代理商： | M3062AFCTGP |
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5. Electrical Characteristics
Rev.2.41
Jan 10, 2006
Page 72 of 96
REJ03B0001-0241
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr =
20 to 85°C / 40 to 85°C unless otherwise specified)
NOTES:
1.
Calculated according to the BCLK frequency as follows:
2.
Calculated according to the BCLK frequency as follows:
n is “2” for 2-wait setting, “3” for 3-wait setting.
3.
Calculated according to the BCLK frequency as follows:
4.
Calculated according to the BCLK frequency as follows:
Table 5.48
Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area
access and multiplex bus selection)
Symbol
Parameter
Standard
Unit
Min.
Max.
td(BCLK-AD)
Address Output Delay Time
See
50
ns
th(BCLK-AD)
Address Output Hold Time (in relation to BCLK)
4
ns
th(RD-AD)
Address Output Hold Time (in relation to RD)
ns
th(WR-AD)
Address Output Hold Time (in relation to WR)
ns
td(BCLK-CS)
Chip Select Output Delay Time
50
ns
th(BCLK-CS)
Chip Select Output Hold Time (in relation to BCLK)
4
ns
th(RD-CS)
Chip Select Output Hold Time (in relation to RD)
ns
th(WR-CS)
Chip Select Output Hold Time (in relation to WR)
ns
td(BCLK-RD)
RD Signal Output Delay Time
40
ns
th(BCLK-RD)
RD Signal Output Hold Time
0
ns
td(BCLK-WR)
WR Signal Output Delay Time
40
ns
th(BCLK-WR)
WR Signal Output Hold Time
0
ns
td(BCLK-DB)
Data Output Delay Time (in relation to BCLK)
50
ns
th(BCLK-DB)
Data Output Hold Time (in relation to BCLK)
4
ns
td(DB-WR)
Data Output Delay Time (in relation to WR)
ns
th(WR-DB)
Data Output Hold Time (in relation to WR)
ns
td(BCLK-HLDA)
HLDA Output Delay Time
40
ns
td(BCLK-ALE)
ALE Signal Output Delay Time (in relation to BCLK)
25
ns
th(BCLK-ALE)
ALE Signal Output Hold Time (in relation to BCLK)
4ns
td(AD-ALE)
ALE Signal Output Delay Time (in relation to Address)
ns
th(AD-ALE)
ALE Signal Output Hold Time (in relation to Address)
ns
td(AD-RD)
RD Signal Output Delay From the End of Address
0
ns
td(AD-WR)
WR Signal Output Delay From the End of Address
0
ns
tdz(RD-AD)
Address Output Floating Start Time
8
ns
0.5x10
9
fBCLK
()
------------------------10 ns
[]
–
0.5x10
9
fBCLK
()
------------------------
50 ns
[]
–
0.5x10
9
fBCLK
()
------------------------
40 ns
[]
–
0.5x10
9
fBCLK
()
------------------------15 ns
[]
–
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