參數(shù)資料
型號(hào): M306N4FGTFP-U0
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù): 82/92頁(yè)
文件大?。?/td> 694K
代理商: M306N4FGTFP-U0
Rev.2.40
Aug 25, 2006
page 83 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4)
5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.25 Timing Diagram (4)
BCLK
CSi
td(BCLK-CS)
30ns.max
ADi
td(BCLK-AD)
30ns.max
ALE
30ns.max
th(BCLK-ALE)
-4ns.min
RD
30ns.max
th(BCLK-RD)
0ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
Hi-Z
DBi
tSU(DB-RD)
50ns.min
th(RD-DB)
0ns.min
tcyc
BHE
Read timing
WR,WRL,
WRH
30ns.max
th(BCLK-WR)
0ns.min
BCLK
CSi
td(BCLK-CS)
30ns.max
ADi
td(BCLK-AD)
30ns.max
ALE
30ns.max
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
tcyc
th(WR-AD)
BHE
td(BCLK-DB)
40ns.max
4ns.min
th(BCLK-DB)
td(DB-WR)
(0.5
tcyc-40)ns.min
(0.5
tcyc-10)ns.min
th(WR-DB)
DBi
Write timing
td(BCLK-ALE)
td(BCLK-RD)
td(BCLK-WR)
0ns.min
th(RD-AD)
tac2(RD-DB)
Hi-Z
Memory Expansion Mode and Microprocessor Mode
(For 1-wait setting and external area access)
(1.5
tcyc-60)ns.max
tcyc =
1
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage
: VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
(0.5
tcyc-10)ns.min
VCC = 3.3 V
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