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| 型號： | M306N4MCV-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 37/92頁 |
| 文件大?。?/td> | 694K |
| 代理商： | M306N4MCV-XXXGP |
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Rev.2.40
Aug 25, 2006
page 42 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4)
5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
ns
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK)
(3)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR)
(3)
__________
HLDA output delay time
Symbol
Parameter
Min.
Standard
Unit
Max.
4
0
(NOTE 1)
4
–4
0
4
(NOTE 2)
(NOTE 1)
Switching Characteristics
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.24 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)
25
15
25
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5
109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n – 0.5)
109
n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting.
f(BCLK)
– 40 [ns]
When n = 1, f(BCLK) is 12.5 MHz or less.
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR
ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 k
, hold time of output “L” level is
t = – 30 pF
1 k ln (1 – 0.2 VCC / VCC) = 6.7 ns.
DBi
R
C
Measuring
Condition
Figure 5.2
VCC = 5 V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M306N4MC-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Renesas MCU |
| M306N4MGT-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Renesas MCU |
| M306N4MGT-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Renesas MCU |
| M306N4MGV-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Renesas MCU |
| M306N4MGV-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Renesas MCU |
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