參數(shù)資料
型號(hào)： M306N5FCFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 57/88頁
文件大小： 683K
代理商： M306N5FCFP
Rev.2.40
Aug 25, 2006
page 60 of 84
REJ03B0004-0240
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
4
(NOTE 1)
4
(NOTE 1)
0
4
(NOTE 2)
(NOTE 1)
–4
(NOTE 3)
(NOTE 4)
0
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
td(AD-RD)
td(AD-WR)
tdZ(RD-AD)
ns
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
Chip select output hold time (in relation to RD)
Chip select output hold time (in relation to WR)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR)
__________
HLDA output delay time
ALE signal output delay time (in relation to BCLK)
ALE signal output hold time (in relation to BCLK)
ALE signal output delay time (in relation to Address)
ALE signal output hold time (in relation to Address)
RD signal output delay from the end of Address
WR signal output delay from the end of Address
Address output floating start time
Symbol
Parameter
Min.
Standard
Unit
Max.
Switching Characteristics
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.50 Memory Expansion Mode and Microprocessor Mode
(for 2- to 3-wait setting, external area access and multiplexed bus selection)
25
40
15
8
Measuring
Condition
Figure 5.12
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5
109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5)
109
f(BCLK)
– 40 [ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
0.5
109
f(BCLK)
– 25 [ns]
4. Calculated according to the BCLK frequency as follows:
0.5
109
f(BCLK)
– 15 [ns]
VCC = 5 V
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