Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
147
Figure 1.16.27 shows the functional block diagram for I2C mode. Setting "1" in the I2C mode selection bit
(IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock
input-output terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission
output, so the SDA output changes after SCL fully goes to "L". An attempt to read Port P71 (SCL) results
in getting the terminal's level regardless of the content of the port direction register. The initial value of
SDA transmission output in this mode goes to the value set in port P70. The interrupt factors of the bus
collision detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the
start/stop condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment
detection interrupt respectively.
The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA
terminal (P70) is detected with the SCL terminal (P71) staying "H". The stop condition detection interrupt
refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the
SCL terminal (P71) staying "H". The bus busy flag (bit 2 of the special UART2 mode register) is set to "1"
by the start condition detection, and set to "0" by the stop condition detection. The acknowledgment non-
detection interrupt refers to the interrupt that occurs when the SDA terminal level is detected still staying
"H" at the rising edge of the 9th transmission clock. The acknowledgment detection interrupt refers to
the interrupt that occurs when SDA terminal's level is detected already went to "L" at the 9th transmis-
sion clock. Also, assigning "1 1 0 1" (UART2 reception) to the DMA1 request cause select bits provides
the means to start up the DMA transfer by the effect of acknowledgment detection.
Bit 1 of the special UART2 mode register (address 01F716) is used as the arbitration lost detecting flag
control bit. Arbitration means the act of detecting the nonconformity between transmission data and
SDA terminal data at the timing of the SCL rising edge. This detecting flag is located at bit 3 of the
UART2 reception buffer register (address 01FF16), and "1" is set in this flag when nonconformity is
detected. Use the arbitration lost detecting flag control bit to choose which way to use to update the flag,
bit by bit or byte by byte. When setting this bit to "1" and updated the flag byte by byte if nonconformity
is detected, the arbitration lost detecting flag is set to "1" at the falling edge of the 9th transmission clock.
If updated the flag byte by byte, must judge and clear ("0") the arbitration lost detecting flag after com-
pleting the first byte acknowledge detect and before starting the next one byte transmission.
Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enabling bit.
Setting this bit to "1" resets the P71 data register to "0" in synchronization with the SCL terminal level
going to "L".
UART2 Special Mode Register