Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
50
Power Control
Clock Monitor Bit (CM23)
The operational status of XIN can be monitored with this bit. When XIN is operating, this bit is "0". After a
clock stop detection, this bit can be polled to check if XIN has restarted. This bit is valid when CM20 is "1".
Reserved Bits (CM24-CM26)
These bits are reserved. They must always remain at "0".
Action Selection (when an oscillation stop is detected) Bit (CM27)
(i) Operation when internal reset is selected (CM27="0")
In case an abnormal stop of XIN is detected when the oscillation stop detection valid bit (CM20) is "1", an
internal reset is generated. The microcomputer stops in reset state, and it does not operate further.
Note: Release from this state is possible by external reset only. However, if XIN clock includes some
errors, further operation cannot be guaranteed.
Table 1.10.6 shows the status of each port after an internal reset is generated.
(ii) Operation when oscillation stop detection interrupt is selected (CM27="1")
In case an abnormal stop of XIN is detected when the oscillation stop detection valid bit (CM20) is "1", an
oscillation stop detection interrupt is generated. In this case, the ring oscillator operates instead of the XIN
stopped abnormally. Further operation can be done to the ring oscillation. Oscillation stop detection inter-
rupt shares the vector table with watchdog timer interrupt. Accordingly, the interrupt factor should be
judged. For this purpose, use the CM22, oscillation stop detection status.
Figure 1.10.10 shows how to judge the factor by the oscillation stop detection interrupt process program.
Stop Mode (CM10="1")
It is recommended the stop detection be disabled before entering stop mode. When returning from stop
mode, the external quartz crystal oscillator is instable for a period of time and may falsely cause a clock
stop to be signalled. It may be enabled again after returning from the stop mode.
Wait Mode (WAIT instruction issued)
When peripheral clocks during wait are enabled (CM02="0"), the oscillation stop/restart detection circuit
can continue to monitor XIN. Should XIN fail, the wait mode is cancelled and an interrupt is generated
(CM27="1"). The microcomputer issues an internal reset if CM27 is "0".
When the wait mode is entered with the peripheral clocks disabled (CM02="1"), the clock stop detection
is disabled. Clock stops will not be detected. The oscillation stop detection circuit will, however, detect
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and react to a stopped clock if the wait mode is cancelled (for instance by an NMI).
Generally, it is recommended to disable the detection circuit before entering wait mode if the peripheral
clocks are to be disabled during wait.