Memory
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
10
0000016
YYYYY16
FFFFF16
0040016
MMMMM16
NNNNN16
XXXXX16
External area
Internal ROM area
SFR area
Internal RAM area
Internal reserved
(Note 2)
area (Note 1)
Internal reserved
area (Note 3)
FFE0016
FFFDC16
FFFFF16
Note 2: Cannot be used in single-chip mode.
Note 1: Cannot be used in any mode.
Note 3: Cannot be used in single-chip mode or memory
expansion mode.
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Oscillation stop detection/Watchdog timer
Reset
Special page
vector table
DBC
NMI
Type No.
Address XXXXX16
Address YYYYY16
M306NBMCT/FCT
017FF16
E000016
M306NAMCT
017FF16
E000016
M306NAMGT
02BFF16
C000016
M306NAFGT
02BFF16
C000016
Note: PM13 (Internal reserved area expansion bit)
PM13 (Note)
Address MMMMM16
Address NNNNN16
0400016
D000016
0600016
C000016
1
0
Figure 1.3.1. Memory map
Operation of Functional Blocks
The M16C/6N group accommodates several units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as CAN module, timers, serial I/O, D-A converter, DMAC, CRC
calculation circuit, A-D converter, and I/O ports.
Each unit is explained in the following.
Memory
Figure 1.3.1 shows the memory map of the M16C/6N group. The address space extends the 1M bytes from
address 0000016 to FFFFF16. The ROM area is mapped top-aligned up to FFFFF16. The start address
depends on the memory capacity of the device; e.g. 128Kbytes ROM are mapped E000016 up to FFFFF16.
______
The vector table for fixed interrupts such as the reset and NMI are mapped to FFFDC16 to FFFFF16. The
starting addresses of the interrupt routines are stored here. The address of the vector table for timer inter-
rupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details.
The RAM area is mapped bottom-aligned starting from 0040016. The end address depends on the RAM
capacity of the device; e.g. 5Kbytes RAM are mapped to 0040016 to 017FF16. In addition to storing data,
the RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph-
eral devices such as I/O ports, A-D converter, serial I/O, CAN modules and timers, etc. Figure 1.6.1 to 1.6.3
show the locations of peripheral unit control registers. Any part of the SFR area that is not occupied is
reserved and cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be implemented as 2-byte instructions, reducing the number of program steps.
Depending on processor mode setting, a part of the space is reserved and cannot be used. For example, in
the M306NAMCT-XXXFP, the following space cannot be used.
The space between 0180016 and 03FFF16 (All modes)
The space between 0400016 and CFFFF16 (Single-chip mode)
The space between D000016 and DFFFF16 (Single-chip mode and memory expansion mode)
For details on how to enable usage of specific memory areas, see the section "Processor Mode".