參數(shù)資料
型號: M306NKFHTGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 68/86頁
文件大?。?/td> 724K
代理商: M306NKFHTGP
Rev.2.10
Aug 25, 2006
page 68 of 81
REJ03B0058-0210
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.17 Timing Diagram (6)
Read timing
Write timing
BCLK
CSi
ALE
DBi
ADi
BHE
WR, WRL
WRH
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting and external area access)
BCLK
CSi
ALE
DBi
ADi
BHE
RD
tcyc
td(BCLK-CS)
30ns.max
td(BCLK-AD)
30ns.max
td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
td(BCLK-RD)
30ns.max
Hi-Z
tSU(DB-RD)
50ns.min
th(RD-DB)
0ns.min
th(BCLK-RD)
0ns.min
th(RD-AD)
0ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
tcyc
Hi-Z
td(BCLK-CS)
30ns.max
td(BCLK-AD)
30ns.max
td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
td(BCLK-WR)
30ns.max
th(BCLK-CS)
4ns.min
th(BCLK-AD)
4ns.min
th(WR-AD)
(0.5
tcyc-10)ns.min
th(BCLK-WR)
0ns.min
td(BCLK-DB)
40ns.max
td(DB-WR)
(2.5
tcyc-40)ns.min
th(BCLK-DB)
4ns.min
th(WR-DB)
(0.5
tcyc-10)ns.min
tac2(RD-DB)
(3.5
tcyc-60)ns.max
tcyc =
1
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage
: VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
VCC = 3.3 V
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