B - 1
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
004016
004116
004216
004316
004416
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
008016
008116
008216
008316
008416
008516
008616
008716
008816
008916
008A16
008B16
008C16
008D16
008E16
008F16
009016
009116
009216
009316
009416
009516
009616
009716
009816
009916
009A16
009B16
009C16
009D16
009E16
009F16
00A016
00A116
00A216
00A316
00A416
Watchdog timer start register
Watchdog timer control register
Processor mode register 0
Address match interrupt register 0
Address match interrupt register 1
Wait control register
System clock control register 0
System clock control register 1
Address match interrupt enable register
Protect register
Processor mode register 1
External data bus width control register
Main clock division register
Address match interrupt register 2
Address match interrupt register 3
Emulator interrupt vector table register
Emulator interrupt detect register
Emulator protect register
ROM areaset register
Debug monitor area set register
Expansion area set register 0
Expansion area set register 1
Expansion area set register 2
Expansion area set register 3
DRAM control register
DRAM refresh interval set register
Timer A1 interrupt control register
UART0 transmit interrupt control register
Timer A0 interrupt control register
Timer A2 interrupt control register
UART0 receive interrupt control register
UART2 transmit/NACK interrupt control register
UART1 receive interrupt control register
DMA2 interrupt control register
DMA0 interrupt control register
Key input interrupt control register
A/D conversion interrupt control register
Bus collision detection(UART3) interrupt control register
UART2 receive/ACK interrupt control register
INT1 interrupt control register
Timer B0 interrupt control register
Timer B2 interrupt control register
Timer A3 interrupt control register
INT2 interrupt control register
INT0 interrupt control register
Timer B1 interrupt control register
Timer A4 interrupt control register
INT3 interrupt control register
Timer B5 interrupt control register
Timer B4 interrupt control register
Timer B3 interrupt control register
INT5 interrupt control register
INT4 interrupt control register
UART3 receive/ACK interrupt control register
UART4 receive/ACK interrupt control register
UART3 transmit/NACK interrupt control register
UART4 transmit/NACK interrupt control register
Exit priority register
UART1 transmit interrupt control register
DMA1 interrupt control register
DMA3 interrupt control register
Bus collision detection(UART2) interrupt control register
Bus collision detection(UART4) interrupt control register
*
Blank spaces are reserved. No access is allowed.
WDTS
WDC
PM0
RMAD0
RMAD1
WCR
CM0
CM1
AIER
PRCR
PM1
DS
MCD
RMAD2
RMAD3
EIAD
EITD
EPRR
ROA
DBA
EXA0
EXA1
EXA2
EXA3
DRAMCONT
REFCNT
TA1IC
S0TIC
TA0IC
TA2IC
S0RIC
S2TIC
S1RIC
DM2IC
DM0IC
KUPIC
ADIC
BCN3IC
S2RIC
INT1IC
TB0IC
TB2IC
TA3IC
INT2IC
INT0IC
TB1IC
TA4IC
INT3IC
TB5IC
TB4IC
TB3IC
INT5IC
INT4IC
S3RIC
S4RIC
S3TIC
S4TIC
RLVL
S1TIC
DM1IC
DM3IC
BCN2IC
BCN4IC
Address
Register
page
Symbol
Address
Register
page
Symbol
27
79
73
40
46
73
55
28
31
47
73
63
183
185
63
49
Quick Reference by Address