
deveopmen
Bus Control
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
32
Table 1.7.6. Operation of RD, WR, and BHE signals
RD
H
L
H
L
H
L
H
L
Status of external data bus
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
BHE
L
L
H
H
L
L
Not used
WR
L
H
L
H
L
H
L
H
Data bus width
A0
H
H
L
L
L
L
H / L
H / L
8-bit
16-bit
Not used
Status of external data bus
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
Write 1 byte of data
Read 1 byte of data
WRH
H
H
L
L
Not used
Not used
WRL
H
L
H
L
L (Note)
RD
L
Data bus width
16-bit
H
H
H
H
L
H (Note)
8-bit
(3) Read/write signals
16
) select the combinations of
RD, BHE, and WR signals or RD, WRL, and WRH signals. With a 8-bit full space data bus, use the
combination of RD, WR, and BHE signals as read/write signals. (Set "0" to bit 2 of the processor mode
register 0 (address 0004
16
).) When using both 8-bit and 16-bit data bus widths and you access an 8-bit
data bus area, the RD, WR and BHE signals combination is selected regardless of the value of bit 2 of the
processor mode register 0 (address 0004
16
).
Tables 1.7.5 and 1.7.6 show the operation of these signals.
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 0004
16
) has been set (Note).
Note 1: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A
16
) to “1”.
Note 2: When using 16-bit data bus width for DRAM controller, select RD, WRL, and WRH signals.
Table 1.7.5. Operation of RD, WRL, and WRH signals
Note: It becomes WR signal.