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參數(shù)資料
| 型號： | M30L0T8000B0ZAQE |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA88 |
| 封裝： | 8 X 10 MM, 0.80 MM PITCH, LEAD FREE, BGA-88 |
| 文件頁數(shù)： | 8/103頁 |
| 文件大小： | 794K |
| 代理商： | M30L0T8000B0ZAQE |
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Signal descriptions
M30L0T8000T0, M30L0T8000B0
2
Signal descriptions
See Figure 1: Logic Diagram and Table 1: Signal Names, for a brief overview of the signals
connected to this device.
2.1
Address Inputs (A-A23)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the Program/Erase Controller.
2.2
Data Input/Output (DQ0-DQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or
input a command or the data to be programmed during a Bus Write operation.
2.3
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active
mode. When Chip Enable is at VIH the memory is deselected, the outputs are high
impedance and the power consumption is reduced to the stand-by level.
2.4
Output Enable (G)
The Output Enable input controls data outputs during the Bus Read operation of the
memory.
2.5
Write Enable (W)
The Write Enable input controls the Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
2.6
Write Protect (WP)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is at VIL, the Lock-Down is enabled and the protection status of the Locked-
Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled
and the Locked-Down blocks can be locked or unlocked. (refer to Table 16: Lock Status).
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