參數(shù)資料
型號： M32171F3VFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
中文描述： 單芯片32位CMOS微機(jī)
文件頁數(shù)： 30/37頁
文件大小： 375K
代理商： M32171F3VFP
Mitsubishi Microcomputers
32171 Group
30
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Figure 17 Block Diagram of Serial I/O
SCLKI0/ SCLKO0
BCLK,
BCLK/8,
BCLK/32,
BCLK/256
Baud rate
generator (BRG)
BCLK
(Set value + 1)
1
I
CSIO mode
When internal clock selected
When UART mode selected
CSIO
mode
UART
mode
When internal clock selected
1/16
1/2
Clock divider
RXD0
TXD0
Receive interrupt
Transmit/receive
control circuit
SIO0 Transmit Buffer Register
SIO0 Transmit Shift Register
Receive DMA transfer request
Transmit interrupt
Transmit DMA transfer request
To DMA3
To DMA4
SIO0 Receive Shift Register
SIO0 Receive Buffer Register
When external clock selected
SIO0
SIO1
SIO2
RXD1
TXD1
SIO1 Transmit Shift Register
SIO1 Receive Shift Register
RXD2
TXD2
To interrupt
controller
Receive interrupt
Transmit/receive
control circuit
Receive DMA transfer request
Transmit interrupt
Transmit DMA transfer request
SCLKI1/ SCLKO1
To DMA6
To DMA3
To interrupt
controller
SIO2 Transmit Shift Register
SIO2 Receive Shift Register
Receive interrupt
Transmit/receive
control circuit
Receive DMA transfer request
Transmit interrupt
Transmit DMA transfer request
To DMA7
To DMA5
To interrupt
controller
Note 1 : When BCLK is selected, the BRG set value is subject to limitations.
Note 2 : SIO2 does not have the SCLKI/SCLKO function.
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