參數(shù)資料
型號(hào)： M34250E2FP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述： 單芯片4位微機(jī)的CMOS
文件頁(yè)數(shù)： 30/58頁(yè)
文件大?。?/td> 331K
代理商： M34250E2FP
MITSUBISHI
ELECTRIC
30
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
LA 4
TV1A
LA 4
TK0A
NOP
SNZ0
NOP
.
.
; (
0
2
)
; The SNZ0 instruction is valid .............
; Change of the interrupt valid waveform
..............................................................
; The SNZ0 instruction is executed
.
.
Fig. 29 External interrupt program example
: this bit is not related to the setting of G
0
/INT pin.
LIST OF PRECAUTIONS
Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
connect a bypass capacitor (approx. 0.01
μ
F) between pins
V
DD
and V
SS
at the shortest distance,
equalize its wiring in width and length, and
use the thickest wire.
In the One Time PROM version, CNV
SS
pin is also used as
V
PP
pin. Connect this pin to V
SS
through the resistor about
5 k
which is assigned to CNV
SS
/V
PP
pin as close as
possible at the shortest distance.
Prescaler
Stop the prescaler operation to change its frequency dividing
ratio.
Timer count source
Stop timer 1 counting to change its count source.
Program counter
Make sure that the PC
H
does not specify after the last page of
the built-in ROM.
G
0
/INT pin
When the interrupt valid waveform of the G
0
/INT pin is changed
with the bit 2 of register K0 in software, be careful about the
following notes.
After clear the bit 0 of register V1 to “0” (Figure 29
),
change the interrupt valid waveform of G
0
/INT pin with the
bit 2 of register K0 .
Set a value to bit 2 of register K0 and execute the SNZ0
instruction to clear the external interrupt request flag (EXF0)
after executing at least one instruction (refer to Figure 29
).
Depending on the input state of the G
0
/INT pin, the EXF0
flag may be set when the interrupt valid waveform is
changed.
Notes on unused pins
When pins G
0
/INT, G
1
/T
OUT
, G
2
and G
3
are connected to
V
SS
pin, turn off their pull-up transistors (register PU0=“
0
2
”)
and also invalidate the key-on wakeup functions of pins
G
1
/T
OUT
, G
2
and G
3
(register K0=“
0
2
”) by software.
When the POF instruction is executed while these pins are
connected to V
SS
and the key-on wakeup functions are left
valid, the system returns from RAM back-up state by
recognizing the return condition immediately after going into
the RAM back-up state. When these pins are open, turn on
their pull-up transistors (register PU0=“
1
2
”) by software.
When ports S
0
–S
3
are connected to V
SS
pin, invalidate the
key-on wakeup functions (register K0=“
0
2
”) by
software. When the POF instruction is executed while these
pins are connected to V
SS
and the key-on wakeup functions
are left valid, the system returns from RAM back-up state
by recognizing the return condition immediately after going
into the RAM back-up state.
When ports D
2
/C and D
3
/K are connected to V
SS
pin, turn
off their pull-up transistors (register PU0=“0
2
”) by software.
When these pins are open, turn on their pull-up transistors
(register PU0=“1
2
”) by software.
(Note when connecting to V
SS
and V
DD
)
Connect the unused pins to V
SS
or V
DD
at the shortest distance
(within 20 mm) and use the thick wire against noise.
Multifunction
G
0
/INT pin can be also used as an I/O port G
0
even when it
is used as INT pin.
G
1
/T
OUT
pin can be also used as input port G
1
even when it
is used as T
OUT
pin.
D
2
/C pin can be also used as I/O port D
2
even when it is
used as port C.
D
3
/K pin can be also used as I/O port D
3
even when it is
used as port K.
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