參數(shù)資料
型號: M34282M2-064GP
廠商: Mitsubishi Electric Corporation
英文描述: Aluminum Electrolytic Capacitor; Capacitor Type:Computer Grade; Voltage Rating:75VDC; Capacitor Dielectric Material:Aluminum Electrolytic; Operating Temperature Range:-40 C to C; Capacitance:68000uF RoHS Compliant: Yes
中文描述: 單芯片4位微機(jī)的CMOS
文件頁數(shù): 39/70頁
文件大?。?/td> 560K
代理商: M34282M2-064GP
4282 Group
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
39
Skip condition
Number of
cycles
Number of
words
Instrunction
code
D
8
D
0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instrunction
code
D
8
D
0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instrunction
code
D
8
D
0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instrunction
code
D
8
D
0
Flag CY
2
16
TAB1
(Transfer data to Accumulator and register B from timer 1)
0
0
1
0
1
0
1
1
1
0
5
7
1
1
Grouping:
Description:
Transfers the contents of timer 1 to regis-
ters A and B.
Timer operation
Operation:
(B)
(T1
7
–T1
4
)
(A)
(T1
3
–T1
0
)
TABE
(Transfer data to Accumulator and register B from register E)
0
0
0
1
0
1
0
1
0
0
2
A
1
1
Grouping:
Description:
Transfers the contents of register E to reg-
isters A and B.
Register to register transfer
Operation:
(B)
(ER
7
–ER
4
)
(A)
(ER
3
–ER
0
)
TABP p
(Transfer data to Accumulator and register B from Program memory in page p)
0
1
0
0
1
p
3
p
2
p
1
p
0
0
9
p
1
3
0/1
Grouping:
Description:
Transfers bits 7 to 4 to register B and bits 3 to 0 to register
A when URS flag is cleared to “0.” These bits 7 to 0 are the
ROM pattern in address (DR
2
DR
1
DR
0
A
3
A
2
A
1
A
0
) speci-
fied by registers A and D in page p.
Transfers bit 8 of ROM pattern is transferred to flag CY when
URS flag is set to “1” (after the URSC instruction is executed).
(One of stack is used when the TABP p instruction is executed.)
Arithmetic operation
Operation:
SK(SP))
(PC) , (SP)
(SP) + 1
(PC
H
)
p, p = 0 to 7, (PC
L
)
(DR
2
–DR
0
, A
3
–A
0
)
When URS = 0,
(B)
(ROM(PC))
7 to 4
, (A)
(ROM(PC))
3 to 0
When URS = 1,
(CY)
(ROM(PC))
8
(B)
(ROM(PC))
7 to 4
, (A)
(ROM(PC))
3 to 0
(SP)
(SP) – 1, (PC)
(SK(SP))
p is 0 to 7 for M34282M1,
p is 0 to 15 for M34282M2/E2.
Note:
TAB2
(Transfer data to Accumulator and register B from timer 2)
0
0
1
0
0
0
0
0
0
0
4
0
1
1
Grouping:
Description:
Transfers the contents of timer 2 to regis-
ters A and B.
Timer operation
Operation:
(B)
(T2
7
–T2
4
)
(A)
(T2
3
–T2
0
)
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