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參數(shù)資料
| 型號： | M34502E4FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, MICROCONTROLLER, PDSO24 |
| 封裝： | 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24 |
| 文件頁數(shù)： | 26/116頁 |
| 文件大?。?/td> | 896K |
| 代理商： | M34502E4FP |
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4502 Group
Rev.3.01
2005.02.02
page 17 of 112
REJ03B0105-0301
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source. An
interrupt occurs when the following 3 conditions are satisfied.
An interrupt activated condition is satisfied (request flag = “1”)
Interrupt enable bit is enabled (“1”)
Interrupt enable flag is enabled (INTE = “1”)
Table 3 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every inter-
rupt enable/disable. Interrupts are enabled when INTE flag is set to
“1” with the EI instruction and disabled when INTE flag is cleared to
“0” with the DI instruction. When any interrupt occurs, the INTE flag
is automatically cleared to “0,” so that other interrupts are disabled
until the EI instruction is executed.
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2
to select the corresponding interrupt or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit and
skip instruction.
Table 5 shows the interrupt enable bit function.
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the cor-
responding interrupt request flag is set to “1.” Each interrupt
request flag is cleared to “0” when either;
an interrupt occurs, or
the next instruction is skipped with a skip instruction.
Each interrupt request flag is set when the activated condition is
satisfied even if the interrupt is disabled by the INTE flag or its in-
terrupt enable bit. Once set, the interrupt request flag retains set
until a clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable state is
released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt dis-
able state is released, the interrupt priority level is as follows
shown in Table 3.
Table 3 Interrupt sources
Activated condition
Level change of INT
pin
Timer 1 underflow
Timer 2 underflow
Completion of
A/D conversion
Priority
level
1
2
3
4
Interrupt name
External 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
A/D interrupt
Table 5 Interrupt enable bit function
Occurrence of interrupt
Enabled
Disabled
Skip instruction
Invalid
Valid
Interrupt enable bit
1
0
Interrupt
address
Address 0
in page 1
Address 4
in page 1
Address 6
in page 1
Address C
in page 1
Table 4 Interrupt request flag, interrupt enable bit and skip in-
struction
Interrupt
request flag
EXF0
T1F
T2F
ADF
Interrupt name
External 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
A/D interrupt
Skip instruction
SNZ0
SNZT1
SNZT2
SNZAD
Interrupt
enable bit
V10
V12
V13
V22
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相關(guān)代理商/技術(shù)參數(shù) |
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| M34506E4 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
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