參數(shù)資料
型號(hào)： M34512M2
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述： 單芯片4位微機(jī)的CMOS
文件頁(yè)數(shù)： 5/80頁(yè)
文件大?。?/td> 760K
代理商： M34512M2
5
4512 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
Notes 1: Pins except above have just single function.
2: The input of P2
0
–P2
2
can be used even when S
CK
, S
OUT
, S
IN
are
selected.
Note: When the P0
0
–P0
3
and P1
0
–P1
3
are connected to V
SS
, turn off their
pull-up transistors (register PU0i=“0”) and also invalidate the key-on
wakeup functions (register K0i=“0”) by software. When these pins are
connected to V
SS
while the key-on wakeup functions are left valid, the
system fails to return from RAM back-up state. When these pins are
open, turn on their pull-up transistors (register PU0i=“1”) by software,
or set the output latch to “0.”
Be sure to select the key-on wakeup functions and the pull-up func-
tions with every two pins. If only one of the two pins for the key-on
wakeup function is used, turn on their pull-up transistors by software
and also disconnect the other pin. (i = 0, 1, 2, or 3.)
(Note when the output latch is set to “0” and pins are open)
G
After system is released from reset, port is in a high-impedance state un-
til it is set the output latch to “0” by software. Accordingly, the voltage
level of pins is undefined and the excess of the supply current may occur
while the port is in a high-impedance state.
G
To set the output latch periodically by software is recommended because
value of output latch may change by noise or a program run away
(caused by noise).
(Note when connecting to V
SS
and V
DD
)
G
Connect the unused pins to V
SS
and V
DD
using the thickest wire at the
shortest distance against noise.
Pin
P2
0
P2
1
P2
2
Multifunction
S
CK
S
OUT
S
IN
MULTIFUNCTION
CONNECTIONS OF UNUSED PINS
Pin
X
OUT
N.F
D
0
–D
7
Connection
Open (when using an external clock).
Connect to V
SS
.
Connect to V
SS
, or set the output latch
to “0” and open.
Connect to V
SS
.
Connect to V
SS
.
Connect to V
SS
.
Open or connect to V
SS
(Note)
Open or connect to V
SS
(Note)
P2
0
/S
CK
P2
1
/S
OUT
P2
2
/S
IN
INT0
INT1
A
IN0
–A
IN3
P0
0
–P0
3
P1
0
–P1
3
Pin
S
CK
S
OUT
S
IN
Multifunction
P2
0
P2
1
P2
2
DEFINITION OF CLOCK AND CYCLE
G
System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the bit 3 of the clock control reg-
ister MR.
Register MR
MR
3
0
1
System clock
f(X
IN
)
f(X
IN
)/2
Note: f(X
IN
)/2 is selected after system is released from reset.
G
Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 3. The one instruction clock cycle generates the one
machine cycle.
G
Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
Table Selection of system clock
PORT FUNCTION
Port
Port D
Port P0
Port P1
Port P2
I/O
unit
1
4
4
3
Control
instructions
SD, RD
SZD
CLD
OP0A
IAP0
OP1A
IAP1
IAP2
Control
registers
PU0, K0
PU0, K0
J1
Output structure
N-channel open-drain
N-channel open-drain
N-channel open-drain
Input
Output
I/O
(8)
I/O
(4)
I/O
(4)
Input
(3)
Remark
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Pin
D
0
–D
7
P0
0
–P0
3
P1
0
–P1
3
P2
0
/S
CK
P2
1
/S
OUT
P2
2
/S
IN
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