參數(shù)資料
型號(hào)： M34513M4-XXXSP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PDIP32
封裝： 0.400 INCH, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁(yè)數(shù)： 37/97頁(yè)
文件大?。?/td> 1276K
代理商： M34513M4-XXXSP
41
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Table 16 Change of successive comparison register AD during A-D conversion
Comparison voltage (Vref) value
Change of successive comparison register AD
At starting conversion
±
(7) Operation description
A-D conversion is started with the A-D conversion start instruction
(ADST). The internal operation during A-D conversion is as follows:
When A-D conversion starts, the register AD is cleared to
“00016.”
Next, the topmost bit of the register AD is set to “1,” and the
comparison voltage Vref is compared with the analog input volt-
age VIN.
When the comparison result is Vref < VIN, the topmost bit of the
register AD remains set to “1.” When the comparison result is
Vref > VIN, it is cleared to “0.”
The 4513/4514 Group repeats this operation to the lowermost bit of
the register AD to convert an analog value to a digital value. A-D
conversion stops after 62 machine cycles (46.5
s when f(XIN) =
4.0 MHz in high-speed mode) from the start, and the conversion re-
sult is stored in the register AD. An A-D interrupt activated condition
is satisfied and the ADF flag is set to “1” as soon as A-D conversion
completes (Figure 27).
1: 1st comparison result
3: 3rd comparison result
9: 9th comparison result
2: 2nd comparison result
8: 8th comparison result
A: 10th comparison result
1st comparison
2nd comparison
3rd comparison
After 10th comparison
completes
1
-----
0
1
2
0
1
3
0
8
0
9
0
A
A-D conversion result
VDD
2
VDD
2
VDD
2
VDD
2
VDD
4
VDD
4
VDD
8
VDD
1024
○○○○
-------------
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