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  • 參數(shù)資料
    型號(hào): M34514M6-263FP
    廠商: Mitsubishi Electric Corporation
    英文描述: SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
    中文描述: 單芯片4位微機(jī)的CMOS
    文件頁數(shù): 26/106頁
    文件大?。?/td> 1304K
    代理商: M34514M6-263FP
    26
    4513/4514 Group
    SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
    MITSUBISHI MICROCOMPUTERS
    PRELIMINARY
    Notice: This is not a final specification.
    change.
    Some parametric limits are subject to
    (3) External interrupt control registers
    Interrupt control register I1
    Register I1 controls the valid waveform for the external 0 inter-
    rupt. Set the contents of this register through register A with the
    TI1A instruction. The TAI1 instruction can be used to transfer the
    contents of register I1 to register A.
    Interrupt control register I2
    Register I2 controls the valid waveform for the external 1 inter-
    rupt. Set the contents of this register through register A with the
    TI2A instruction. The TAI2 instruction can be used to transfer the
    contents of register I2 to register A.
    Table 8 External interrupt control registers
    I1
    3
    I1
    2
    I1
    1
    I1
    0
    I2
    3
    I2
    2
    I2
    1
    I2
    0
    Not used
    Interrupt valid waveform for INT0 pin/
    return level selection bit (Note 2)
    INT0 pin edge detection circuit control bit
    INT0 pin
    timer 1 control enable bit
    This bit has no function, but read/write is enabled.
    Falling waveform (“L” level of INT1 pin is recognized with the SNZI1
    instruction)/“L” level
    Rising waveform (“H” level of INT1 pin is recognized with the SNZI1
    instruction)/“H” level
    One-sided edge detected
    Both edges detected
    Disabled
    Enabled
    Not used
    Interrupt valid waveform for INT1 pin/
    return level selection bit (Note 3)
    INT1 pin edge detection circuit control bit
    INT1 pin
    timer 3 control enable bit
    Notes 1: “R” represents read enabled, and “W” represents write enabled.
    2: When the contents of I1
    2
    is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.
    3: When the contents of I2
    2
    is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
    Interrupt control register I1
    R/W
    at RAM back-up : state retained
    at reset : 0000
    2
    This bit has no function, but read/write is enabled.
    Falling waveform (“L” level of INT0 pin is recognized with the SNZI0
    instruction)/“L” level
    Rising waveform (“H” level of INT0 pin is recognized with the SNZI0
    instruction)/“H” level
    One-sided edge detected
    Both edges detected
    Disabled
    Enabled
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    Interrupt control register I2
    R/W
    at RAM back-up : state retained
    at reset : 0000
    2
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