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參數(shù)資料
| 型號(hào)： | M34551M8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER |
| 中文描述： | 單芯片4位CMOS微機(jī)紅外遙控器 |
| 文件頁(yè)數(shù)： | 59/68頁(yè) |
| 文件大小： | 698K |
| 代理商： | M34551M8 |
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59
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
CONTROL REGISTERS (CONTINUED)
I1
3
I1
2
I1
1
I1
0
Not used
Interrupt valid waveform for INT pin
selection bit (Note 2)
Not used
Not used
0
1
0
1
0
1
0
1
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Interrupt control register I1
R/W
at reset : 0000
2
at power down : state retained
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Port P1
3
pull-up transistor
control bit
Port P1
2
pull-up transistor
control bit
Port P1
1
pull-up transistor
control bit
Port P1
0
pull-up transistor
control bit
0
1
0
1
0
1
0
1
at reset : 0000
2
at power down : state retained
Pull-up control register PU0
R/W
PU0
3
PU0
2
PU0
1
PU0
0
System clock (STCK) selection bit
f(X
CIN
) oscillation circuit control bit
f(X
IN
) oscillation circuit control bit
Clock selection bit
at reset : 1000
2
at power down : state retained
Clock control register MR
R/W
MR
3
MR
2
MR
1
MR
0
MR
0
=0 f(X
IN
)
MR
0
=1 f(X
CIN
)
MR
0
=0 f(X
IN
)/4
MR
0
=1 f(X
CIN
)/4
f(X
CIN
) oscillation stop, ports D
6
and D
7
selected
f(X
CIN
) oscillation enabled, ports D
6
and D
7
not selected
Oscillation enabled
Oscillation stop
f(X
IN
)
f(X
CIN
)
0
1
0
1
0
1
0
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Depending on the input state of D
5
/INT pin, the external interrupt request flag EXF0 may be set to “1” when the contents of
I1
2
is changed. Accordingly, set a value to bit 2 of register I1 and execute the SNZ0 instruction to clear the EXF0 flag after
executing at least one instruction.
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