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Rev.3.02
Dec 22, 2006
page 68 of 142
REJ03B0025-0302
4556 Group
CONTROL REGISTERS
I13
I12
I11
I10
INT pin input control bit (Note 2)
Interrupt valid waveform for INT pin/
return level selection bit (Note 3)
INT pin edge detection circuit control bit
INT pin Timer 1 count start synchronous
circuit selection bit
Interrupt control register I1
R/W
TAI1/TI1A
at power down : state retained
at reset : 00002
INT pin input disabled
INT pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
instruction)
One-sided edge detected
Both edges detected
Timer 1 count start synchronous circuit not selected
Timer 1 count start synchronous circuit selected
0
1
0
1
0
1
0
1
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
V13
V12
V11
V10
V23
V22
V21
V20
Not used
Timer 3 interrupt enable bit
Interrupt control register V2
at power down : 00002
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V1
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
Not used
External 0 interrupt enable bit
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
0
1
0
1
0
1
0
1
at power down : 00002
at reset : 00002
R/W
TAV1/TV1A
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag (EXF0) may be set.
3: The stopped clock cannot be selected for system clock.
4: “11” cannot be set to the low-order 2 bits (MR1, MR0) of register MR.
R/W
TAV2/TV2A
MR3
Clock control register MR
Operation mode
Through mode
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
System clock
f(RING)
f(XIN)
f(XCIN)
Not available (Note 4)
at reset : 11002
at power down : state retained
MR3
0
1
MR1
0
1
R/W
TAMR/
TMRA
Operation mode selection bits
MR2
0
1
0
1
MR0
0
1
0
1
MR2
MR3
System clock selection bits (Note 3)
MR2