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參數(shù)資料
| 型號： | M34570EDFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片4位微機的CMOS |
| 文件頁數(shù)： | 25/68頁 |
| 文件大?。?/td> | 319K |
| 代理商： | M34570EDFP |
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25
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a
program runs wild. Watchdog timer consists of 16-bit timer (WDT),
watchdog timer enable flag (WEF), and watchdog timer flags
(WDF1, WDF2).
Timer WDT starts downcounting the instruction clocks as the
count source immediately after system is released from reset.
The underflow signal is generated when the count value reaches
“0000
16
.” This underflow signal can be used as the timer 2 count
source.
When the WRST instruction is executed after system is released
from reset, the WEF flag is set to “1.” At this time, the watchdog
timer starts operating.
When the count value of timer WDT reaches “BFFF
16
” or
“3FFF
16
,” WDF1 flag is set to “1.” Then, if the WRST instruction
is not executed while the timer WDT counts 32767, the WDF2
flag is set to “1” and the
RESET
pin outputs “L” level to reset the
microcomputer. In software using the watchdog timer, make sure
that the WRST instruction is executed in 32766 machine cycles
or less in order to keep the microcomputer operating normally.
To prevent the watchdog timer from stopping in the event of
misoperation, the WEF flag is designed not to be initialized once
the WRST instruction has been executed. Note also that, if the
WRST instruction is never executed, the watchdog timer does
not start.
Fig. 20 Watchdog timer function
Fig. 21 Program example to enter the RAM back-up mode
when using the watchdog timer
Value of timer WDT
Flag WDF2
RESET pin output
System reset
WRST instruction
execution
Flag WEF
FFFF
16
0000
16
Flag WDF1
3FFF
16
BFFF
16
WRST instruction
execution
The contents of the WEF flag, the WDF1 and WDF2 flags and
the timer WDT are initialized at the RAM back-up mode.
However, if the WDF2 flag is set to “1” at the same time that the
microcomputer enters the RAM back-up mode, system reset may
be performed.
When using the watchdog timer and the RAM back-up mode,
initialize the WDF1 flag with the WRST instruction just before
the microcomputer enters the RAM back-up mode (refer to Figure
21).
WRST ; Clear WDF1 flag
POF
EPOF ; POF instruction execution enabled
(RAM back-up mode)
Oscillation stop
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