參數(shù)資料
型號： M34570M4-227FP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述： 單芯片4位微機的CMOS
文件頁數(shù)： 14/68頁
文件大?。?/td> 319K
代理商： M34570M4-227FP
14
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Program counter (PC)
..................................................... Each interrupt address
Stack register (SK)
...........
The address of main routine to be executed when returning
Interrupt enable flag (INTE)
........................................................ 0 (Interrupt disabled)
Interrupt request flag (only the flag for the current interrupt source)
........................................................................................ 0
Data pointer, carry flag, registers A and B, skip flag
...............
Stored in the interrupt stack register (SDP) automatically
Fig. 13 Program example of interrupt processing
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is
as follows (Figure 14).
Program counter (PC)
An interrupt address is set in program counter. The
address to be executed when returning to the main routine
is automatically stored in the stack register (SK).
Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
Interrupt request flag
Only the request flag for the current interrupt source is
cleared to “0.”
Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored
automatically in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address
is executed after a branch to a sequence for storing data into
stack register is performed. Write the branch instruction to
an interrupt service routine at an interrupt address.
Use the RTI instruction to return to main routine.
Interrupt enabled by executing the EI instruction is performed
after executing 1 instruction (just after the next instruction is
executed). Accordingly, when the EI instruction is executed
just before the RTI instruction, interrupts are enabled after
returning to the main routine. (Refer to Figure 13)
Fig. 14 Internal state when interrupt occurs
Fig. 15 Interrupt system diagram
EI
RTI
Interrupt
service routine
Interrupt
occurs
Interrupt
is enabled
Main
routine
: Interrupt enabled state
: Interrupt disabled state
T1F
V1
2
EXF0
V1
0
Address 4 in
page 1
Address 0 in
page 1
T2F
V1
3
Address 6 in
page 1
Timer 1
underflow
Request
flag
(state retained)
Enable
bit
Enable
flag
Activated
condition
INT pin
(L
→
H or
H
→
L input)
INTE
Timer 2
underflow
T3F
V2
0
Timer 3
underflow
Address 8 in
page 1
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