參數(shù)資料
型號(hào)： M34570M8
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述： 單芯片4位微機(jī)的CMOS
文件頁(yè)數(shù)： 3/68頁(yè)
文件大?。?/td> 319K
代理商： M34570M8
3
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PERFORMANCE OVERVIEW
Parameter
Number of basic instructions
Minimum instruction execution time
Function
99
1.5
μ
s (f(X
IN
) = 2.0 MHz:system clock = f(X
IN
): V
DD
= 5.0 V)
2.86
μ
s (f(X
IN
) = 4.2 MHz:system clock = f(X
IN
)/4: V
DD
= 5.0 V)
4096 words
10 bits
8192 words
10 bits
16384 words
10 bits
8192 words
10 bits
16384 words
10 bits
128 words
4 bits
Ten independent output ports; port D
9
is also used as the T
OUT
output pin.
4-bit I/O port; every pin of the ports has a key-on wakeup function and a pull-up function.
4-bit I/O port; every pin of the ports has a key-on wakeup function and a pull-up function.
2-bit input port, port P2
1
is also used as INT input pin.
4-bit I/O port
4-bit input port; both pull-up function and key-on wakeup function can be switched by software.
1-bit output port (CMOS output)
1-bit output pin; T
OUT
output pin is also used as port D
9
.
1-bit input pin with a key-on wakeup function. INT input pin is also used as port P2
1
.
10-bit timer with a reload register and carrier wave output auto-control function
8-bit timer with a reload register
8-bit timer with two reload registers and carrier wave generation function
4 (one for external and three for timer)
1 level
8 levels (however, only 7 levels can be used when an interrupt is used or the TABP p instruction
is executed)
CMOS silicon gate
36-pin plastic molded SSOP
–20
°
C to 70
°
C
2.0 V to 5.5 V for mask ROM version (2.5 V to 5.5 V for One Time PROM version)
1.3 mA (f(X
IN
) = 4.2 MHz: system clock = f(X
IN
)/4, V
DD
=5.0 V)
0.5 mA (f(X
IN
) = 1.0 MHz: system clock = f(X
IN
), V
DD
=3.0 V)
0.1
μ
A (Ta=25
°
C, V
DD
=5V, typical value)
Memory sizes
Input/Output
ports
Timers
Interrupt
Subroutine nesting
Device structure
Package
Operating temperature range
Supply voltage
Power
dissipation
(typical value)
ROM
RAM
D
0
–D
9
P0
0
–P0
3
P1
0
–P1
3
P2
0
, P2
1
P3
0
–P3
3
P4
0
–P4
3
CARR
T
OUT
INT
Timer 1
Timer 2
Timer 3
Sources
Nesting
at active
at RAM back-up
M34570M4
M34570M8
M34570MD
M34570E8
M34570ED
Output
I/O
I/O
Input
I/O
Input
Output
Output
Input
DEFINITION OF CLOCK AND CYCLE
G
System clock
The system clock is the basic clock for controlling this product.
The system clock can be selected by bit 3 of the clock control
register MR as shown in the table below.
Table Selection of system clock
MR
3
0
1
Note: f(X
IN
)/4 is selected immediately after system is released
from reset.
G
Instruction clock
The instruction clock is the standard clock for controlling CPU.
The instruction clock is a signal derived from dividing the
system clock by 3. The one cycle of the instruction clock is
equivalent to the one machine cycle.
G
Machine cycle
The machine cycle is the standard cycle required to execute
the instruction.
System clock
f(X
IN
)
f(X
IN
)/4
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