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參數資料
| 型號： | M34D64MNT5 |
| 廠商： | 意法半導體 |
| 元件分類： | DRAM |
| 英文描述： | 64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory |
| 中文描述： | 64/32千位串行IC總線EEPROM，帶有硬件寫控制記憶的熱門季 |
| 文件頁數： | 10/15頁 |
| 文件大?。?/td> | 119K |
| 代理商： | M34D64MNT5 |
M34D64, M34D32
10/15
Table 9. AC Characteristics
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This is preliminary data.
Symbol
Alt.
Parameter
M34D64 / M34D32
Unit
V
CC
=4.5 to 5.5 V
T
A
=0 to 70°C or
–40 to 85°C
V
CC
=2.5 to 5.5 V
T
A
=0 to 70°C or
–40 to 85°C
V
CC
=1.8 to 3.6 V
T
A
=0 to 70°C or
–20 to 85°C
4
Min
Max
Min
Max
Min
Max
t
CH1CH2
t
R
Clock Rise Time
300
300
1000
ns
t
CL1CL2
t
F
Clock Fall Time
300
300
300
ns
t
DH1DH2 2
t
R
SDA Rise Time
20
300
20
300
20
1000
ns
t
DL1DL2 2
t
F
SDA Fall Time
20
300
20
300
20
300
ns
t
CHDX 1
t
SU:STA
Clock High to Input Transition
600
600
4700
ns
t
CHCL
t
HIGH
Clock Pulse Width High
600
600
4000
ns
t
DLCL
t
HD:STA
Input Low to Clock Low (START)
600
600
4000
ns
t
CLDX
t
HD:DAT
Clock Low to Input Transition
0
0
0
μs
t
CLCH
t
LOW
Clock Pulse Width Low
1.3
1.3
4.7
μs
t
DXCX
t
SU:DAT
Input Transition to Clock
Transition
100
100
250
ns
t
CHDH
t
SU:STO
Clock High to Input High (STOP)
600
600
4000
ns
t
DHDL
t
BUF
Input High to Input Low (Bus
Free)
1.3
1.3
4.7
μs
t
CLQV 3
t
AA
Clock Low to Data Out Valid
200
900
200
900
200
3500
ns
t
CLQX
t
DH
Data Out Hold Time After Clock
Low
200
200
200
ns
f
C
f
SCL
Clock Frequency
400
400
100
kHz
t
W
t
WR
Write Time
10
10
10
ms
Table 10. AC Measurement Conditions
Input Rise and Fall Times
≤
50 ns
Input Pulse Voltages
0.2V
CC
to 0.8V
CC
Input and Output Timing
Reference Voltages
0.3V
CC
to 0.7V
CC
Figure 9. AC Testing Input Output Waveforms
AI00825
0.8VCC
0.2VCC
0.7VCC
0.3VCC
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