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參數(shù)資料
| 型號： | M34S32WMN6T |
| 廠商： | 意法半導體 |
| 元件分類： | DRAM |
| 英文描述： | 32K Serial I2C Bus EEPROM With User-Defined Read-Only Block and 32-Byte OTP Page |
| 中文描述： | 32K的串行I2C總線的EEPROM與用戶定義的只讀塊和32字節(jié)檢察官頁 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大小： | 156K |
| 代理商： | M34S32WMN6T |
14/18
M34S32
Sequence A:
Start
OTP Page Select(= 1010 001
0
)
Ack
Address MSB
Ack
Address LSB
Ack
Sequence B:
Start
OTP Page Select(= 1010 001
1
)
Ack
Data
Ack
........
Data
(no Ack)
Stop
If one, or more bits of the Sequence A differ from
the above values, the bytes that follow it will be ac-
knowledged (or not) according to the same rules
as for the WRITE IN OTP, and the RANDOM AD-
DRESS READ IN OTP will be ignored.
Sequential Read.
This mode can be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se-
quence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-
put, but MUST generate a STOP condition.
The output data is from consecutive byte ad-
dresses, with the internal byte address counter au-
tomatically incremented after each byte output. Af-
ter a count of the last memory address, the
address counter will “roll-over” and the memory
will continue to output data.
A Sequential Read in the OTP page is performed
by sending the appropriate Device Select Byte, as
described in Table 3. If a sequential read reaches
the last location in the OTP page (address 1Fh),
subsequent Sequential Reads will wrap round to
the start, to address 00h.
Acknowledge in Read Mode.
In all read modes
the memory waits for an acknowledge during the
9th bit time. If the master does not pull the SDA
line low during this time, the memory terminates
the data transfer and switches to a stand-by state.
(= xxxx 0000)
(= 000x xxxx)
APPLICATION HINTS ON HOW TO USE THE
CONTROL REGISTER TOGETHER WITH THE /
WCR PIN
The application board can be designed in such a
way that WCR pin is connected to V
SS
(directly or
through a pull-down resistor). It should be noted
that the WCR pin features an internal pull-down re-
sistor allowing this input to be left unconnected.
With such a P.C.B. (Printed Circuit Board), the de-
vice can be initialised according to following set-up
sequence :
1. Write the data that is to be Write protected:
– Write data in the area starting from address
00h up to the desired address.
2. Write in the Control Register (single byte write
using the following bits):
– Set B2, B1 and B0 values according to the
ROM block size (as defined in Table 15)
– Set WCpol according to the application
needs.
– Set CRWD bit to 1
Once the CRWD bit is set to 1, the control register
becomes Write Protected. The only way to write
again to the Control Register is to set the WCR pin
high. This is possible by applying V
CC
to WCR if it
was previously floating or connected to V
SS
through an external pull-down resistor. If WCR is
shorted to V
SS
, the device needs to be de-sol-
dered from the PCB.
OTHER NOTES
The WCR pin has an internal pull-down resistor.
Connecting this pin to GND does not affect the
power consumption, thus giving the M34S32 its
lowest power consumption when it is in Protected
mode.
The OTP page may be programmed before or af-
ter the hardware protected mode has been set (by
setting the CRWD bit). This allows the application
MCU to program the OTP page either on the as-
sembly line or during the operating life of the appli-
cation.
The WC pin (but not the WCR pin) may be driven
dynamically by the MCU to increase the immunity
to data corruption of the unprotected EEPROM ar-
ea. This pin may alternatively be pulled to V
CC
or
GND (depending on which is appropriate, accord-
ing to the setting of the WCpol bit).
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