參數(shù)資料
型號: M36L0R7040T0ZAQF
廠商: 意法半導(dǎo)體
英文描述: 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 16 Mbit PSRAM, 1.8V Supply, Multi-Chip Package
中文描述: 128兆位(多銀行,多層次,突發(fā))閃存和16兆移動存儲芯片,1.8V電源,多芯片封裝
文件頁數(shù): 4/18頁
文件大?。?/td> 119K
代理商: M36L0R7040T0ZAQF
M36L0R7040T0, M36L0R7040B0
4/18
SUMMARY DESCRIPTION
The M36L0R7040T0 and M36L0R7040B0 com-
bine two memory devices in a Multi-Chip Package:
a 128-Mbit, Multiple Bank Flash memory, the
M30L0R7000T0 or M30L0R7000B0, and a 16-
Mbit PseudoSRAM, the M69AR024B. Recom-
mended operating conditions do not allow more
than one memory to be active at the same time.
The memory is offered in a Stacked TFBGA88
(8x10mm, 8x10 ball array, 0.8mm pitch) package.
In addition to the standard version, the packages
are also available in Lead-free version, in compli-
ance with JEDEC Std J-STD-020B, the ST ECO-
PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free solder-
ing processes.
The memory is supplied with all the bits erased
(set to ‘1’).
Figure 2. Logic Diagram
Table 1. Signal Names
Note: 1. A22-A20 are not connected to the PSRAM component.
AI08467
23
A0-A22
DQ0-DQ15
M36L0R7040T0
M36L0R7040B0
G
F
16
W
F
RP
F
WP
F
E1
P
G
P
W
P
UB
P
LB
P
VSS
V
DDF
V
PPF
V
DDP
WAIT
F
L
F
K
F
V
DDQ
E
F
E2
P
A0-A22
(1)
Address Inputs
DQ0-DQ15
Common Data Input/Output
V
DDF
Power Supply for Flash Memory
V
DDQ
Flash Memory Power Supply for I/O
Buffers
V
PPF
Flash Optional Supply Voltage for Fast
Program and Erase
V
SS
Ground
V
DDP
PSRAM Power Supply
NC
Not Connected Internally
DU
Do Not Use as Internally Connected
Flash Memory Control Functions
L
F
Latch Enable Input
E
F
Chip Enable Input
G
F
Output Enable Input
W
F
Write Enable Input
RP
F
Reset Input
WP
F
Write Protect Input
K
F
Burst Clock
WAIT
F
Wait Data in Burst Mode
PSRAM Control Functions
E1
P
Chip Enable Input
G
P
Output Enable Input
W
P
Write Enable Input
E2
P
Power-down Input
UB
P
Upper Byte Enable Input
LB
P
Lower Byte Enable Input
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