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參數(shù)資料
| 型號(hào)： | M36L0R7040T0ZAQT |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 16 Mbit PSRAM, 1.8V Supply, Multi-Chip Package |
| 中文描述： | 128兆位（多銀行，多層次，突發(fā)）閃存和16兆移動(dòng)存儲(chǔ)芯片，1.8V電源，多芯片封裝 |
| 文件頁(yè)數(shù)： | 9/18頁(yè) |
| 文件大?。?/td> | 119K |
| 代理商： | M36L0R7040T0ZAQT |
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M36L0R7040T0, M36L0R7040B0
Table 2. Main Operating modes
Note: 1. X = Don't care.
2. L
F
can be tied to V
IH
if the valid address has been previously latched.
3. Depends on G
F
.
4. WAIT signal polarity is configured using the Set Configuration Register command. See the M30L0R7000T0 datasheet for details.
Operation
E
F
G
F
W
F
L
F
RP
F
WAIT
F
(4)
E1
P
E2
P
G
P
W
P
LB
P
,UB
P
DQ15-DQ0
Flash Read
V
IL
V
IL
V
IH
V
IL(2)
V
IH
PSRAM must be disabled
Flash Data Out
Flash Write
V
IL
V
IH
V
IL
V
IL(2)
V
IH
Flash Data In
Flash Address
Latch
V
IL
X
V
IH
V
IL
V
IH
Flash Data Out
or Hi-Z
(3)
Flash Output
Disable
V
IL
V
IH
V
IH
X
V
IH
Any PSRAM mode is allowed
Hi-Z
Flash Standby
V
IH
X
X
X
V
IH
Hi-Z
Hi-Z
Flash Reset
X
X
X
X
V
IL
Hi-Z
Hi-Z
PSRAM Read
Flash Memory must be disabled
V
IL
V
IH
V
IL
V
IH
V
IL
PSRAM data
out
PSRAM Write
V
IL
V
IH
V
IH
V
IL
V
IL
PSRAM data in
Output Disable
Any Flash mode is allowed
V
IL
V
IH
V
IH
V
IH
X
Hi-Z
PSRAM
Standby
V
IH
V
IH
X
X
X
Hi-Z
PSRAM Deep
Power-Down
X
V
IL
X
X
X
Hi-Z
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| M36L0R7040U1Z85U | 制造商:STMicroelectronics 功能描述: |
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| M36L0R7050 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32 Mbit (2M x16) PSRAM, 1.8V Supply Multi-Chip Package |
| M36L0R7050B0 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32 Mbit (2M x16) PSRAM, 1.8V Supply Multi-Chip Package |
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