參數(shù)資料
型號: M36W0R6050T1ZAQE
廠商: 意法半導(dǎo)體
英文描述: 64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 】16) PSRAM, multi-chip package
中文描述: 64兆位(4兆】16日,多銀行,突發(fā))閃存和32兆位(2字節(jié)】16)移動存儲芯片,多芯片封裝
文件頁數(shù): 6/22頁
文件大?。?/td> 159K
代理商: M36W0R6050T1ZAQE
Description
M36W0R6050T1, M36W0R6050B1
6/22
1
Description
The M36W0R6050T1 and M36W0R6050B1 combine two memories in a Multi-Chip
Package:
a 64-Mbit, Multiple Bank Flash memory, the M58WR064HT/B, and
a 32-Mbit Pseudo SRAM, the M69KB048BD.
The purpose of this document is to describe how the two memory components operate with
respect to each other. It must be read in conjunction with the M58WR064HT/B and
M69KB048BD datasheets, where all specifications required to operate the Flash memory
and PSRAM components are fully detailed. These datasheets are available from the ST web
site:
www.st.com
.
Recommended operating conditions do not allow more than one memory to be active at the
same time.
The memory is offered in a Stacked TFBGA88 (8 ×10 mm, 8 × 10 ball array, 0.8 mm pitch)
package. It is supplied with all the bits erased (set to ‘1’).
Figure 1.
Logic diagram
Ai12035
22
A0-A21
DQ0-DQ15
M36W0R6050T1
M36W0R6050B1
G
F
16
W
F
RP
F
WP
F
E1
P
G
P
W
P
UB
P
LB
P
VSS
V
DDF
V
PPF
V
DDP
WAIT
F
L
F
K
F
V
DDQF
E
F
E2
P
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