參數(shù)資料
型號(hào): M36W108AT120ZM5T
廠商: 意法半導(dǎo)體
英文描述: 8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product
中文描述: 8兆1兆× 8,啟動(dòng)塊閃存和1兆位128KB的x8 SRAM的低電壓多媒體存儲(chǔ)產(chǎn)品
文件頁數(shù): 18/35頁
文件大?。?/td> 247K
代理商: M36W108AT120ZM5T
M36W108T, M36W108B
18/35
Table 18. Flash Write AC Characteristics, Write Enable Controlled
(T
A
= 0 to 70 °C, –20 to 85 °C or –40 to 85 °C; V
CCF
= 2.7V to 3.6V)
Note: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Symbol
Alt
Parameter
Flash Memory Chip
Unit
100
120
C
L
= 30pF
C
L
= 100pF
Min
Max
Min
Max
t
AVAV
t
WC
Address Valid to Next Address Valid
100
120
ns
t
ELWL
t
CS
Chip Enable Low to Write Enable Low
0
0
ns
t
WLWH
t
WP
Write Enable Low to Write Enable High
50
50
ns
t
DVWH
t
DS
Input Valid to Write Enable High
50
50
ns
t
WHDX
t
DH
Write Enable High to Input Transition
0
0
ns
t
WHEH
t
CH
Write Enable High to Chip Enable High
0
0
ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low
30
30
ns
t
AVWL
t
AS
Address Valid to Write Enable Low
0
0
ns
t
WLAX
t
AH
Write Enable Low to Address Transition
50
50
ns
t
GHWL
Output Enable High to Write Enable Low
0
0
ns
t
VCHEL
t
VCS
V
CC
High to Chip Enable Low
50
50
μs
t
WHGL
t
OEH
Write Enable High to Output Enable Low
0
0
ns
t
PHPHH
(1,2)
t
VIDR
RP Rise Time to V
ID
500
500
ns
t
PLPX
t
RP
RP Pulse Width
500
500
ns
t
WHRL
(1)
t
BUSY
Program Erase Valid to RB Delay
90
90
ns
t
PHWL
(1)
t
RSP
RP High to Write Enable Low
4
4
μs
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