參數(shù)資料
型號(hào): M36W108B100ZM5T
廠商: 意法半導(dǎo)體
英文描述: 8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product
中文描述: 8兆1兆× 8,啟動(dòng)塊閃存和1兆位128KB的x8 SRAM的低電壓多媒體存儲(chǔ)產(chǎn)品
文件頁數(shù): 8/35頁
文件大?。?/td> 247K
代理商: M36W108B100ZM5T
M36W108T, M36W108B
8/35
Instructions are composed of up to six cycles. The
first two cycles input a Coded Sequence to the
Command Interface which is common to all in-
structions (see Table 9). The third cycle inputs the
instruction set-up command. Subsequent cycles
output the addressed data or Electronic Signature
for Read operations. In order to give additional
data protection, the instructions for Program and
Block or Chip Erase require further command in-
puts. For a Program instruction, the fourth com-
mand cycle inputs the address and data to be
programmed. For an Erase instruction (block or
chip), the fourth and fifth cycles input a further
Coded Sequence before the Erase confirm com-
mand on the sixth cycle. Erasure of a memory
block may be suspended, in order to read data
from another block or to program data in another
block, and then resumed.
When power is first applied or if V
CCF
falls below
V
LKO
, the command interface is reset to Read Ar-
ray.
Command sequencing must be followed exactly.
Any invalid combination of commands will reset
the device to Read Array. The increased number
of cycles has been chosen to assure maximum
data security.
Read/Reset (RD) Instruction.
The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded cycles. Subsequent read opera-
tions will read the memory array addressed and
output the data read. A wait state of t
PLYH
is nec-
essary after Read/Reset prior to any valid read if
the memory was in an Erase or Program mode
when the RD instruction is given (see Table 17
and Figure 9).
Auto Select (AS) Instruction.
This
uses the two Coded cycles followed by one write
cycle giving the command 90h to address 5555h
for command set-up. A subsequent read will out-
put the Manufacturer Code or the Device Code
(Electronic Signature) depending on the levels of
A0 and A1 (see Table 7). The Electronic Signature
can be read from the memory allowing program-
ming equipment or applications to automatically
match their interface to the characteristics of the
Flash memory. The Manufacturer Code, 20h, is
output when the addresses lines A0 and A1 are at
V
IL
, the Device Code is output when A0 is at V
IH
with A1 at V
IL
. Other address inputs are ignored.
Program (PG) Instruction.
This instruction uses
four write cycles. The Program command A0h is
written to address 5555h on the third cycle after
two Coded Cycles. A fourth write operation latch-
es the Address and the Data to be written and
starts the P/E.C. Read operations output the Sta-
tus Register bits after the programming has start-
ed. Memory programming is made only by writing
’0’ in place of ’1’. Status bits DQ6 and DQ7 deter-
mine if programming is on-going and DQ5 allows
verification of any possible error. Programming at
an address not in blocks being erased is also pos-
sible during erase suspend. In this case, DQ2 will
toggle at the address being programmed.
instruction
Table 8. Flash Commands
Hex Code
Command
00h
Invalid/Reserved
10h
Chip Erase Confirm
20h
Reserved
30h
Block Erase Resume/Confirm
80h
Set-up Erase
90h
Read Electronic Signature/
Block Protection Status
A0h
Program
B0h
Erase Suspend
F0h
Read Array/Reset
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