參數(shù)資料
型號(hào)： M36W108T120ZM6T
廠商： 意法半導(dǎo)體
英文描述： Coaxial Cable; Coaxial RG/U Type:6; Impedance:75ohm; Conductor Size AWG:18; No. Strands x Strand Size:Solid; Jacket Material:FEP; Jacket Color:Blue; Leaded Process Compatible:Yes; Voltage Nom.:30V RoHS Compliant: Yes
中文描述： 8兆1兆× 8，啟動(dòng)塊閃存和1兆位128KB的x8 SRAM的低電壓多媒體存儲(chǔ)產(chǎn)品
文件頁(yè)數(shù)： 9/35頁(yè)
文件大小： 247K
代理商： M36W108T120ZM6T
9/35
M36W108T, M36W108B
Block Erase (BE) Instruction.
This
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 5555h
on third cycle after the two Coded cycles. The
Block Erase Confirm command 30h is similarly
written on the sixth cycle after another two Coded
Cycles. During the input of the second command
an address within the block to be erased is given
and latched into the memory.
Additional block Erase Confirm commands and
block addresses can be written subsequently to
erase other blocks in parallel, without further Cod-
ed cycles. The erase will start after the erase tim-
eout period (see Erase Timer Bit DQ3 description).
Thus, additional Erase Confirm commands for oth-
er blocks must be given within this delay. The input
of a new Erase Confirm command will restart the
timeout period. The status of the internal timer can
be monitored through the level of DQ3, if DQ3 is ’0’
the Block Erase Command has been given and
the timeout is running, if DQ3 is ’1’, the timeout has
expired and the P/E.C. is erasing the block(s). If
the second command given is not an erase con-
firm or if the Coded cycles are wrong, the instruc-
tion aborts, and the device is reset to Read Array.
It is not necessary to program the block with 00h
as the P/E.C. will do this automatically before to
erasing to FFh. Read operations after the sixth ris-
ing edge of W or EF output the Status Register
bits.
During the execution of the erase by the P/E.C.,
the memory only accepts the Erase Suspend (ES)
and Read/Reset (RD) instructions. A Read/Reset
command will definitively abort erasure and result
in invalid data in blocks being erased. A complete
state of the block erase operation is given by the
Status Register bits (see DQ2, DQ3, DQ5, DQ6
and DQ7 description).
Chip Erase (CE) Instruction.
This
uses six write cycles. The Erase Set-up command
80h is written to address 5555h on the third cycle
after the two Coded Cycles. The Chip Erase Con-
firm command 10h is similarly written on the sixth
cycle after another two Coded Cycles. If the sec-
instruction
instruction
ond command given is not an erase confirm or if
the Coded Sequence is wrong, the instruction
aborts and the device is reset to Read Array. It is
not necessary to program the array with 00h first
as the P/E.C. will automatically do this before
erasing it to FFh. Read operations after the sixth
rising edge of W or EF output the Status Register
bits. A complete state of the chip erase operation
is given by the Status Register bits (see DQ2,
DQ3, DQ5, DQ6 and DQ7 description).
Erase Suspend (ES) Instruction.
The
Erase operation may be suspended by this in-
struction which consists of writing the command
B0h without any specific address. No Coded Cy-
cles are required. It permits reading of data from
another block and programming in another block
while an erase operation is in progress. Erase sus-
pend is accepted only during the Block Erase in-
struction execution. Writing this command during
the erase timeout period will, in addition to sus-
pending the erase, terminate the timeout. The
Toggle bit DQ6 stops toggling when the P/E.C. is
suspended. The Toggle bits will stop toggling be-
tween 0.1μs and 15μs after the Erase Suspend
(ES) command has been written. The device will
then automatically be set to Read Memory Array
mode. When erase is suspended, a Read from
blocks being erased will output DQ2 toggling and
DQ6 at '1'. A Read from a block not being erased
returns valid data. During suspension the memory
will respond only to the Erase Resume (ER) and
the Program (PG) instructions. A Program opera-
tion can be initiated during Erase Suspend in one
of the blocks not being erased. It will result in both
DQ2 and DQ6 toggling when the data is being pro-
grammed. A Read/Reset command will definitively
abort erasure and result in invalid data in the
blocks being erased.
Erase Resume (ER) Instruction.
If an Erase
Suspend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at any address, and without any
Coded cycles.
Block
相關(guān)PDF資料
PDF描述
M36W108B120ZM6T Coaxial Cable; Coaxial RG/U Type:6; Impedance:75ohm; Conductor Size AWG:18; No. Strands x Strand Size:Solid; Jacket Material:FEP; Conductor Material:Copper; Jacket Color:Black; Leaded Process Compatible:Yes; Number of Conductors:1 RoHS Compliant: Yes
M36W108TZN 8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product
M36W108BZM 8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product
M36W108BZN 8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product
M36W108TZM 8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M36W108T120ZN1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product
M36W108T120ZN5T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product
M36W108T120ZN6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product
M36W108TZM 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product
M36W108TZN 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product
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