- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄45029 > M37161MA-XXXSP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 PDF資料下載
參數(shù)資料
| 型號(hào)： | M37161MA-XXXSP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42 |
| 文件頁(yè)數(shù)： | 62/129頁(yè) |
| 文件大?。?/td> | 1092K |
| 代理商： | M37161MA-XXXSP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)當(dāng)前第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)
Rev.1.00
2003.11.25
page 38 of 128
M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
8.6.8 START/STOP Condition Detect Conditions
The START/STOP condition detect conditions are shown in
Figure 8.6.12 and Table 8.6.3. Only when the 3 conditions of Table
8.6.3 are satisfied, a START/STOP condition can be detected.
Note: When a STOP condition is detected in the slave mode
(MST = 0), an interrupt request signal “IICIRQ” is generated to the
CPU.
Fig. 8.6.12 START Condition/STOP Condition Detect Timing
Diagram
Standard Clock Mode
6.5
s (26 cycles) < SCL
release time
3.25
s (13 cycles) < Setup time
3.25
s (13 cycles) < Hold time
High-speed Clock Mode
1.0
s (4 cycles) < SCL
release time
0.5
s (2 cycles) < Setup time
0.5
s (2 cycles) < Hold time
Table 8.6.3 START Condition/STOP Condition Detect Conditions
Note: Absolute time at
φ = 4 MHz. The value in parentheses denotes the num-
ber of
φ cycles.
Hold time
Setup
time
SCL
SDA
(START condition)
SDA
(STOP condition)
SCL release time
Hold time
Setup
time
8.6.9 Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective ad-
dress communication formats are described below.
(1) 7-bit addressing format
To support the 7-bit addressing format, set the 10BIT SAD bit of the
I2C control register (address 00F916) to “0.” The first 7-bit address
data transmitted from the master is compared with the high-order 7-
bit slave address stored in the I2C address register (address 00F716).
At the time of this comparison, address comparison of the RBW bit of
the I2C address register (address 00F716) is not made. For the data
transmission format when the 7-bit addressing format is selected,
refer to Figure 8.6.13, (1) and (2).
(2) 10-bit addressing format
To support the 10-bit addressing format, set the 10BIT SAD bit of the
I2C control register (address 00F916) to “1.” An address comparison
is made between the first-byte address data transmitted from the
master and the 7-bit slave address stored in the I2C address register
(address 00F716). At the time of this comparison, an address com-
parison is performed between the RBW bit of the I2C address regis-
____
ter (address 00F716) and the R/W bit, which is the last bit of the
address data transmitted from the master. In the 10-bit addressing
____
mode, the R/W bit not only specifies the direction of communication
for control data but is also processed as an address data bit.
When the first-byte address data matches the slave address, the
AAS bit of the I2C status register (address 00F816) is set to “1.” After
the second-byte address data is stored into the I2C data shift register
(address 00F616), perform an address comparison between the sec-
ond-byte data and the slave address by software. When the address
data of the 2nd byte matches the slave address, set the RBW bit of
the I2C address register (address 00F716) to “1” by software. This
processing can match the 7-bit slave address and R/W data, which
are received after a RESTART condition is detected, with the value
of the I2C address register (address 00F716). For the data transmis-
sion format when the 10-bit addressing format is selected, refer to
Figure 8.6.13, (3) and (4).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37161M8-XXXSP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
| M37202E3SP | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP64 |
| M37207EFFP | 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PQFP80 |
| M37207MF-XXXSP | 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP64 |
| M37207M8-XXXSP | 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37161MF-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37161MF-XXXSP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M3720 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND |
| M3720-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND |
| M3720-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。