參數(shù)資料
型號： M37212M8-XXXSP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
中文描述： 單芯片8位CMOS微機電壓合成
文件頁數(shù)： 40/119頁
文件大?。?/td> 1308K
代理商： M37212M8-XXXSP
40
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
M37212M4/M8–XXXSP, M37212M6–XXXSP/FP
M37212EFSP/FP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
8.6.8 START/STOP Condition Detect Conditions
The START/STOP condition detect conditions are shown in
Figure 8.6.11 and Table 8.6.3. Only when the 3 conditions of Table
8.6.3 are satisfied, a START/STOP condition can be detected.
Note:
When a STOP condition is detected in the slave mode
(MST = 0), an interrupt request signal “IICIRQ” is generated to the
CPU.
Fig. 8.6.11 START Condition/STOP Condition Detect Timing Dia-
gram
Standard Clock Mode
6.5
μ
s (26 cycles) < SCL
release time
3.25
μ
s (13 cycles) < Setup time
3.25
μ
s (13 cycles) < Hold time
High-speed Clock Mode
1.0
μ
s (4 cycles) < SCL
release time
0.5
μ
s (2 cycles) < Setup time
0.5
μ
s (2 cycles) < Hold time
Table 8.6.3 START Condition/STOP Condition Detect Conditions
Note:
Absolute time at
φ
= 4 MHz. The value in parentheses denotes the num-
ber of
φ
cycles.
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8.6.9 Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective ad-
dress communication formats is described below.
(1) 7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the I
2
C
control register (address 00DA
16
) to “0.” The first 7-bit address data
transmitted from the master is compared with the high-order 7-bit
slave address stored in the I
2
C address register (address 00D8
16
).
At the time of this comparison, address comparison of the RBW bit of
the I
2
C address register (address 00D8
16
) is not made. For the data
transmission format when the 7-bit addressing format is selected,
refer to Figure 8.6.12, (1) and (2).
(2) 10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the
I
2
C control register (address 00DA
16
) to “1.” An address comparison
is made between the first-byte address data transmitted from the
master and the 7-bit slave address stored in the I
2
C address register
(address 00D8
16
). At the time of this comparison, an address com-
parison between the RBW bit of the I
2
C address register (address
00D8
16
) and the R/W bit which is the last bit of the address data
transmitted from the master is made. In the 10-bit addressing mode,
the R/W bit which is the last bit of the address data not only specifies
the direction of communication for control data but also is processed
as an address data bit.
When the first-byte address data matches the slave address, the
AAS bit of the I
2
C status register (address 00D9
16
) is set to “1.” After
the second-byte address data is stored into the I
2
C data shift register
(address 00D7
16
), make an address comparison between the sec-
ond-byte data and the slave address by software. When the address
data of the 2nd bytes matches the slave address, set the RBW bit of
the I
2
C address register (address 00D8
16
) to “1” by software. This
processing can match the 7-bit slave address and R/W data, which
are received after a RESTART condition is detected, with the value
of the I
2
C address register (address 00D8
16
). For the data transmis-
sion format when the 10-bit addressing format is selected, refer to
Figure 8.6.12, (3) and (4).
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