參數(shù)資料
型號: M37221EFSP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
中文描述: 單芯片8位CMOS微機電壓合成與屏幕顯示控制器
文件頁數(shù): 4/61頁
文件大?。?/td> 1386K
代理商: M37221EFSP
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
4
Power source
CNV
SS
Reset input
Clock input
Clock output
I/O port P0
PWM output
External interrupt
input
Analog input
I/O port P1
CRT output
Multi-master
I
2
C-BUS interface
Analog input
External interrupt
input
I/O port P2
External clock input
Serial I/O synchro-
nizing clock input/
output
Serial I/O data
input/output
I/O port P3
Analog input
Input port P3
Clock input for
CRT display
Clock output for
CRT display
V
CC
,
V
SS.
CNV
SS
RESET
X
IN
X
OUT
P0
0
/PWM0–
P0
5
/PWM5,
P0
6
/INT2/
A-D4
,
P0
7
/INT1
P1
0
/OUT2,
P1
1
/SCL1,
P1
2
/SCL2,
P1
3
/SDA1,
P1
4
/SDA2,
P1
5
/A-D1/
INT3,
P1
6
/A-D2,
P1
7
/A-D3
P2
0
/S
CLK
,
P2
1
/S
OUT
,
P2
2
/S
IN
,
P2
3
/TIM3,
P2
4
/TIM2,
P2
5
–P2
7
P3
0
/A-D5,
P3
1
/A-D6,
P3
2
P3
3
/OSC1,
P3
4
/OSC2
Input
Input
Output
I/O
Output
Input
Input
I/O
Output
I/O
Input
Input
I/O
Input
I/O
I/O
I/O
Input
Input
Input
Output
Apply voltage of 5 V ± 10 % (typical) to V
CC
, and 0 V to V
SS
.
This is connected to V
SS
.
To enter the reset state, the reset input pin must be kept at a “L” for 2
μ
s or more (under
normal V
CC
conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should
be maintained for the required time.
This chip has an internal clock generating circuit. To control generating frequency, an
external ceramic resonator or a quartz-crystal oscillator is connected between pins X
IN
and
X
OUT
. If an external clock is used, the clock source should be connected to the X
IN
pin and
the X
OUT
pin should be left open.
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
is N-channel open-drain output. The note out of this Table gives a full of port P0 function.
Pins P0
0
–P0
5
are also used as PWM output pins PWM0–PWM5 respectively. The output
structure is N-channel open-drain output.
Pins P0
6
, P0
7
are also used as external interrupt input pins INT2, INT1 respectively.
P0
6
pin is also used as analog input pin A-D4.
Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.
Pins P1
0
is also used as CRT output pin OUT2. The output structure is CMOS output.
Pins P1
1
–P1
4
are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master
I
2
C-BUS interface is used. The output structure is N-channel open-drain output.
Pins P1
5
–P1
7
are also used as analog input pins A-D1 to A-D3 respectively.
P1
5
pin is also used as external interrupt input pin INT3.
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.
Pins P2
3
, P2
4
are also used as external clock input pins TIM3, TIM2 respectively.
P2
0
pin is also used as serial I/O synchronizing clock input/output pin S
CLK
.
Pins P2
1
, P2
2
are also used as serial I/O data input/output pins S
OUT
, S
IN
respectively.
The output structure is N-channel open-drain output.
Ports P3
0
–P3
2
are a 3-bit I/O port and has basically the same functions as port P0. Either
CMOS output or N-channel open-drain output structure can be selected as the port P3
0
and P3
1
. The output structure of port P3
2
is N-channel open-drain output.
Pins P3
0
, P3
1
are also used as analog input pins A-D5, A-D6 respectively.
Ports P3
3
, P3
4
are a 2-bit input port.
P3
3
pin is also used as CRT display clock input pin OSC1.
P3
4
pin is also used as CRT display clock output pin OSC2. The output structure is CMOS
output.
PIN DESCRIPTION
Pin
Name
Functions
Input/
Output
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