參數(shù)資料
型號: M37221EFSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDIP42
封裝: 0.600 INCH, 1.778 MM PITCH, SHRINK, PLASTIC, DIP-42
文件頁數(shù): 15/63頁
文件大?。?/td> 1371K
代理商: M37221EFSP
M37221EF-XXXSP,M37221EFSP
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
22
ACK
BIT
FAST
MODE
CCR4 CCR3 CCR2 CCR1 CCR0
I2C clock control register
(S2 : address 00DB16)
70
SCL frequency
control bits
Refer to Table 3.
SCL mode
specification bit
0 : Standard clock
mode
1 : High-speed clock
mode
ACK bit
0 : ACK is returned.
1 : ACK is not returned.
ACK clock bit
0 : No ACK clock
1 : ACK clock
Table 3. Set values of I2C clock control register and SCL frequency
(4) I2C Control Register
The I2C control register (address 00DA16) controls data communica-
tion format.
s Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. An interrupt request signal occurs immediately after the
number of bits specified with these bits are transmitted.
When a START condition is received, these bits become “0002” and
the address data is always transmitted and received in 8 bits.
s Bit 3: I2C interface use enable bit (ES0)
This bit enables to use the multimaster I2C BUS interface. When this
bit is set to “0,” the use disable status is provided, so the SDA and
the SCL become high-impedance. When the bit is set to “1,” use of
the interface is enabled.
When ES0 = “0,” the following is performed.
PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2C
status register at address 00D916 ).
Writing data to the I2C data shift register (address 00D716) is dis-
abled.
s Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses. When
this bit is set to “0,” the addressing format is selected, so that ad-
dress data is recognized. When a match is found between a slave
address and address data as a result of comparison or when a gen-
eral call (refer to “(5) I2C Status Register,” bit 1) is received, trans-
mission processing can be performed. When this bit is set to “1,” the
free data format is selected, so that slave addresses are not recog-
nized.
s Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is
set to “0,” the 7-bit addressing format is selected. In this case, only
the high-order 7 bits (slave address) of the I2C address register (ad-
dress 00D816) are compared with address data. When this bit is set
to “1,” the 10-bit addressing format is selected, all the bits of the I2C
address register are compared with address data.
s Bits 6 and 7: Connection control bits between I2C-BUS interface
and ports (BSEL0, BSEL1)
These bits controls the connection between SCL and ports or SDA
and ports (refer to Figure 17).
SCL frequency
(at
φ = 4MHz, unit : kHz)
Setting value of
CCR4–CCR0
Standard clock
mode
Setting disabled
100
83.3
500/CCR value
17.2
16.6
16.1
High-speed clock
mode
Setting disabled
333
250
400(Note)
166
1000/CCR value
34.5
33.3
32.3
CCR4
0
1
CCR3
0
1
CCR2
0
1
CCR1
0
1
0
1
0
1
CCR0
0
1
0
1
0
1
0
1
0
1
Note: At 400 kHz in the high-speed clock mode, the duty is 40%.
In the other cases, the duty is 50%.
Fig. 16. Structure of I2C clock control register
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