參數(shù)資料
型號(hào)： M37221M6-286SP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
中文描述： 單芯片8位CMOS微機(jī)電壓合成
文件頁數(shù)： 9/61頁
文件大小： 1386K
代理商： M37221M6-286SP
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
9
INTERRUPTS
Interrupts can be caused by 14 different sources consisting of 4 ex-
ternal, 8 internal, 1 software, and reset. Interrupts are vectored inter-
rupts with priorities shown in Table 1. Reset is also included in the
table because its operation is similar to an interrupt.
When an interrupt is accepted,
(1) The contents of the program counter and processor status
register are automatically stored into the stack.
(2) The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
(3) The jump destination address stored in the vector address enters
the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figure 4 shows the structure of
the interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are ac-
cepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 5 shows interrupt control.
Interrupt Causes
(1) V
SYNC
and CRT interrupts
The V
SYNC
interrupt is an interrupt request synchronized with
the vertical sync signal.
The CRT interrupt occurs after character block display to the CRT
is completed.
(2) INT1, INT2, INT3 interrupts
With an external interrupt input, the system detects that the level
of a pin changes from “L” to “H” or from “H” to “L,” and generates
an interrupt request. The input active edge can be selected by
bits 3, 4 and 5 of the interrupt input polarity register (address
00F9
16
) : when this bit is “0,” a change from “L” to “H” is de-
tected; when it is “1,” a change from “H” to “L” is detected. Note
that all bits are cleared to “0” at reset.
(3) Timer 1, 2, 3 and 4 interrupts
An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial
I/O function.
(5) f(X
IN
)/4096 interrupt
This interrupt occurs regularly with a f(X
IN
)/4096 period. Set bit 0
of the PWM output control register 1 to “0.”
(6) Multi-master I
2
C-BUS interface interrupt
This is an interrupt request related to the multimaster I
2
C-BUS
interface.
(7) BRK instruction interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not af-
fected by the interrupt disable flag I (non-maskable).
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Vector addresses
FFFF
16
, FFFE
16
FFFD
16
, FFFC
16
FFFB
16
, FFFA
16
FFF9
16
, FFF8
16
FFF5
16
, FFF4
16
FFF3
16
, FFF2
16
FFF1
16
, FFF0
16
FFEF
16
, FFEE
16
FFED
16
, FFEC
16
FFEB
16
, FFEA
16
FFE9
16
, FFE8
16
FFE7
16
, FFE6
16
FFE5
16
, FFE4
16
FFDF
16
, FFDE
16
Interrupt source
Reset
CRT interrupt
INT2 interrupt
INT1 interrupt
Timer 4 interrupt
f(X
IN
)/4096 interrupt
V
SYNC
interrupt
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
Serial I/O interrupt
Multi-master I
2
C-BUS interface interrupt
INT3 interrupt
BRK instruction interrupt
Remarks
Non-maskable
Active edge selectable
Active edge selectable
Active edge selectable
Active edge selectable
Non-maskable (software interrupt)
Table 1. Interrupt vector addresses and priority
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