參數(shù)資料
型號(hào)： M37270MF-106SP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁(yè)數(shù)： 41/94頁(yè)
文件大?。?/td> 1551K
代理商： M37270MF-106SP
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
41
7
MST
0
I
2
C status register
(S1 : address 00F8
16
)
Last receive bit (Note)
0 : Last bit = “0”
1 : Last bit = “1”
General call detecting flag
(Note)
0 : No general call detected
1 : General call detected
Slave address comparison flag
(Note)
0 : Address disagreement
1 : Address agreement
Arbitration lost detecting flag
(Note)
0 : Not detected
1 : Detected
I
2
C-BUS interface interrupt
request bit
0 : Interrupt request issued
1 : No interrupt request
issued
Bus busy flag
0 : Bus free
1 : Bus busy
Communication mode
specification bits
00 : Slave receive mode
01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
TRX BB PIN AL
AAS AD0 LRB
Note:
These bit and flags can be read out but cannot
be written.
(6) START Condition Generating Method
When the ES0 bit of the I
2
C control register (address 00F9
16
) is “1,”
execute a write instruction to the I
2
C status register (address 00F8
16
)
for setting the MST, TRX and BB bits to “1.” Then a START condi-
tion occurs. After that, the bit counter becomes “000
2
” and an SCL
for 1 byte is output. The START condition generating timing and BB
bit set timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 43, the START condition generat-
ing timing diagram, and Table 8, the START condition/STOP condi-
tion generating timing table.
(7) STOP Condition Generating Method
When the ES0 bit of the I
2
C control register (address 00F9
16
) is “1,”
execute a write instruction to the I
2
C status register (address 00F8
16
)
for setting the MST bit and the TRX bit to “1” and the BB bit to “0”.
Then a STOP condition occurs. The STOP condition generating tim-
ing and the BB flag reset timing are different in the standard clock
mode and the high-speed clock mode. Refer to Figure 44, the STOP
condition generating timing diagram, and Table 8, the START condi-
tion/STOP condition generating timing table.
Table 8. START condition/STOP condition generating timing
table
Item
Setup time
Hold time
Set/reset time
for BB flag
Fig. 43. START condition generating timing diagram
Fig. 44. STOP condition generating timing diagram
Fig. 42. Interrupt request signal generating timing
Fig. 41. Structure of I
2
C status register
SCL
PIN
IICIRQ
I
2
C status register
write signal
BB flag
AAA
Hold time
time
Setup
SCL
SDA
BB flag
Setup
time
I
2
C status register
write signal
Reset time for
BB flag
AAA
time
Hold time
Setup
SCL
SDA
BB flag
Standard clock mode
5.0
μ
s (20 cycles)
5.0
μ
s (20 cycles)
3.0
μ
s (12 cycles)
High-speed clock mode
2.5
μ
s (10 cycles)
2.5
μ
s (10 cycles)
1.5
μ
s (6 cycles)
Note:
Absolute time at
φ
= 4 MHz. The value in parentheses de-
notes the number of
φ
cycles.
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