參數(shù)資料
型號(hào)： M37271EF-XXXSP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁(yè)數(shù)： 45/97頁(yè)
文件大小： 1436K
代理商： M37271EF-XXXSP
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
45
Fig. 48. START condition/STOP condition detecting timing
diagram
(8) START/STOP Condition Detecting Condi-
tions
The START/STOP condition detecting conditions are shown in Fig-
ure 48 and Table 9. Only when the 3 conditions of Table 9 are satis-
fied, a START/STOP condition can be detected.
Note:
When a STOP condition is detected in the slave mode
(MST = 0), an interrupt request signal “IICIRQ” occurs to the
CPU.
(9) Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective ad-
dress communication formats is described below.
1
7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the
I
2
C control register (address 00F9
16
) to “0.” The first 7-bit address
data transmitted from the master is compared with the high-order
7-bit slave address stored in the I
2
C address register (address
00F7
16
). At the time of this comparison, address comparison of
the RBW bit of the I
2
C address register (address 00F7
16
) is not
made. For the data transmission format when the 7-bit address-
ing format is selected, refer to Figure 49, (1) and (2).
2
10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the
I
2
C control register (address 00F9
16
) to “1.” An address compari-
son is made between the first-byte address data transmitted from
the master and the 7-bit slave address stored in the I
2
C address
register (address 00F7
16
). At the time of this comparison, an ad-
dress comparison between the RBW bit of the I
2
C address regis-
ter (address 00F7
16
) and the R/W bit which is the last bit of the
address data transmitted from the master is made. In the 10-bit
addressing mode, the R/W bit which is the last bit of the address
data not only specifies the direction of communication for control
data but also is processed as an address data bit.
AAA
Hold time
AAA
Setup
time
SCL
SDA
(START condition)
SDA
(STOP condition)
SCL release time
Setup
time
Standard clock mode
6.5
μ
s (26 cycles) <
SCL
release time
3.25
μ
s (13 cycles) < Setup time
3.25
μ
s (13 cycles) < Hold time
Note:
Absolute time at
φ
= 4 MHz. The value in parentheses de-
notes the number of
φ
cycles.
High-speed clock mode
1.0
μ
s (4 cycles) <
SCL
release time
0.5
μ
s (2 cycles) < Setup time
0.5
μ
s (2 cycles) < Hold time
Table 9. START condition/STOP condition detecting conditions
Fig. 49. Address data communication format
S
Slave address
A
Data
A
Data
A/A
P
R/W
7 bits
“0”
1 to 8 bits
1 to 8 bits
S
Slave address
A
Data
A
Data
A
P
7 bits
“1”
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S
Slave address
1st 7 bits
A
A
Data
7 bits
“0”
8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
Slave address
2nd byte
A
Data
A/A
P
1 to 8 bits
S
Slave address
1st 7 bits
A
A
7 bits
“0”
8 bits
7 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
Slave address
2nd byte
Data
1 to 8 bits
Sr
Slave address
1st 7 bits
A
Data
A
P
1 to 8 bits
“1”
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
From master to slave
From slave to master
A
R/W
R/W
R/W
R/W
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