7470/7471/7477/7478 GROUP USER’S MANUAL
1-174
HARDWARE
1.18 State transitions
s Reset
→ Ordinary mode (State A)
Immediately after reset, the main clock divided by 2 (f(XIN)/2) is selected as an internal clock
φ and
the I/O pins XCIN and XCOUT of the sub-clock f(XCIN) become ordinary ports. “FF16” and “0716” are
set in timer 3 and timer 4 respectively, and also the main clock divided by 16 (f(XIN)/16) is selected
as a count source of timer 3 and the overflow signal of timer 3 is selected as a count source of
timer 4. Then a down-count is started.
When timer 4 overflows, the internal reset is released and the program starts from the address
specified by reset vector.
s Low-speed mode (Stae C and state D)
To the low-speed mode (state C and state D) using the sub-clock divided by 2 (f(XCIN)/2) as an
internal clock
φ, a transition is made by way of the ordinary mode (state A)
state B (
state
C).
In the 7470/7477 group, which is not provided with a sub-clock oscillation circuit, this mode is not
provided.
s Wait mode (State E)
In this mode, all the states of registers, I/O ports and internal RAMs are held. The internal clock
φ stops at “H” but the oscillator does not stop.
From any of state A, state B, state C and state D, a return is made to the wait mode by executing
the WIT instruction. When a return is made from the state D to the wait mode, the sub-clock mode
in which only the timer function operates is provided. (In the 7470/7477 group, which is not
provided with a sub-clock oscillation circuit, the sub-clock mode is not provided.)
Refer to “1.17.2 Wait mode.”
s Stop mode (State F)
In this mode, all the states of registers, I/O ports and internal RAMs except timer 3 and timer 4
are held and the oscillation of both main sub-clock is stopped. From any of state A, B, C and D,
a return is made to the stop mode by executing the STP instruction.
Refer to “1.17.1 Stop mode.”
s Sub-clock mode (State G)
Only the clock-function is made to operate by sub-clock mode at low-power dissipation.
The sub-clock mode (state G) is provided by executing the WIT instruction in the low-speed mode
(state D), and restoration from this state to the low-speed mode is attached by each interrupt.
In the 7470/7477 group, which is not provided with a sub-clock oscillation circuit, this mode is not
provided.