7480 Group and 7481 Group User's Manual
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HARDWARE
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Notes on Usage of UART
Pay attention to the following notes when UART is selected.
Selecting BRG output/16 as Synchronous Clock
Since the SCLK pin is not used to output the synchronous clock to the external, the P16/SCLK pin can
be used as normal port pin P16.
Selecting External Clock/16 Input as Synchronous Clock
Keep the HIGH- and the LOW- width (TWH and TWL) of the pulses used as the external clock source
TWH, TWL [s]
≥ (2/f(XIN) [Hz]). For example, use a frequency of 2 MHz or less (50% duty cycle) as
the external clock source when f(XIN) = 8 MHz.
Handling Recovering from Errors Generated
Handling when parity error or framing error is generated
When the parity error or the framing error occurs, the flag corresponding to each error and the
summing error flag of the serial I/O status register are set to ‘1’. To clear these flags to ‘0’, perform
either of the following operations.
Clear the receive enable bit of the serial I/O control register to ‘0’.
Write dummy data to the serial I/O status register.
Handling when overrun error is generated
If the next data is stored completely in the receive shift register before the data transferred from
the receive shift register to the receive buffer register is read through, the overrun error is generated.
At this time, the overrun error flag and the summing error flag of the serial I/O status register are
set to ‘1’. The contents of the receive shift register are not transferred to the receive buffer
register, so that the contents of the receive buffer register remain unaffected. As a result, if the
contents of the receive buffer register are read, the data of the receive shift register is not transferred
to the receive buffer register and becomes invalid.
When the overrun error occurs, clear the overrun error flag to ‘0’ by any of the following operations
and perform receive preparation again.
Clear the serial I/O enable bit of the serial I/O control register to ‘0’. (In this case, only the
overrun error flag returns to ‘0’.)
Clear the receive enable bit of the serial I/O control register to ‘0’.
Write dummy data into the serial I/O status register.
Referring to Transmit Shift Completion Flag
The transmit shift completion flag changes from ‘1’ to ‘0’ with a delay of 0.5 to 1.5 clocks of the
synchronous clock. Therefore, pay attention to this delay when data transmission is controlled, by
referring to the transmit shift completion flag after the transmit data is written to the transmit buffer
register.
1.14 Serial I/O