
7480 Group and 7481 Group User's Manual
1-166
1.19 Power Saving Function
HARDWARE
1.19.2 Stop Mode
(1)
Operations in Stop Mode
State in Stop Mode
When the STP instruction is valid, its execution causes the CPU to enter the stop mode. In this
mode, the CPU operation is halted because internal clock
φ stops in the HIGH state. In addition, the
operation of the peripherals stops as well, because the oscillation of f(XIN) stops. As a result, power
dissipation can be reduced.
Timer 1 goes to ‘FF16’ to generate the oscillator start-up stabilization time necessary for terminating
the stop mode, and a frequency of f(XIN)/8 is selected as the count source.
Note: Timers continue counting in the event count mode, as done the serial I/O does when the
external clock (or its 1/16) is selected as the synchronous clock.
For the operations in the stop mode, refer to Table 1.19.1 States of Microcomputer in Power
Saving Modes.
The stop mode is terminated by reset or accepting an interrupt request, and the CPU returns to the
normal mode.
The operation at recovery from the stop mode by reset or accepting an interrupt request is described
below.
Recovery from Stop Mode by Reset Input
By applying the LOW level to the RESET pin for 2
s or more in the stop mode, the CPU enters
the reset state and is brought out of the stop mode, causing the XIN oscillation to resume.
When the RESET pin is restored to the HIGH level, the oscillator start-up stabilization time is
generated by timer 1.
After the oscillator start-up stabilization time elapses, internal clock
φ is supplied to the CPU.
The program is executed at the address stored in the reset vector area.
Figure 1.19.5 shows the operation at recovery from the stop mode by reset input.
Figure 1.19.5 Operation at Recovery from Stop Mode by Reset Input
For details of reset, refer to Section 1.17 Reset.
VCC
XIN pin
RESET
Undefined
Internal reset
Stop mode
STP instruction
executed
Stop mode is terminated
by reset input
2
s
or more
Note: 2 cycles of internal clock
Oscillation start-up stabilization time
2048 cycles of XIN pin input signal
XIN pin : High-impedance state
STP instruction execution cycle (Note)
φ