7480 Group and 7481 Group User's Manual
1-31
HARDWARE
1.10 Input/Output Pins
(1)
Port Pi Registers (i = 0 to 5)
Each port register can read the states of the port pins and specify the output levels of them.
Pin used for input (Ports P0 to P5)
A read: When reading from port register corresponding to each port, the input value (state of the
pin) is read; the contents of port latch is not read.
A write: When writing to port register corresponding to each port, data is written only into the port
latch; the state of the pin is unaffected.
Pin used for output (Ports P0, P1, P4, and P5)
A read: When reading from port register corresponding to each port, the written value into the port
latch is read; the state of the pin is not read. Therefore, even if the output voltage is
affected by the external load etc., the last output value can correctly be read.
A write: When writing to port register corresponding to each port, data written into a bit of the port
register can be output to the external circuit through the output transistor.
Note: The 7480 Group does not have port P5 and, consequently, is not provided with the port P5
register.
Figure 1.10.5 shows the port Pi registers (i = 0 to 5).
Figure 1.10.5 Port Pi Registers (i = 0 to 5)
Port Pi (i=0 to 5)
b5
b6
b7
b4 b3 b2 b1 b0
b
Function
R
W
1
2
3
4
5
6
7
0
Port Pi (Pi, i=0 to 5) [Addresses 00C016,00C216,00C416,00C616,00C816,00CA16]
Note: In the 7480 Group, port P2 has only bits 0 to 3. The other bits are not implemented. (undefined at reading).
When used as input ports (Ports P0 to P5)
At reading, input level of pin is read.
At writing, writing to port latch is performed and
the pin state is not affected.
When used as output ports (Ports P0, P1, P4, P5)
At reading, the last written value into the port latch is
read.
At writing, the written value is output externally through
a transistor.
At reset
Undefined
O
Port P3 has only bits 0 to 3. The other bits are not implemented (‘0’ at reading).
In the 7480 Group, port P4 has only bits 0 and 1. In the 7481 Group, port P4 has only bits 0 to 3.
The other bits are not implemented. (bits 4 to 7: ‘0’ at reading, bits 2 and 3 in the 7480 Group: undefined).
The 7480 Group does not have port P5. In the 7481 Group, port P5 has only bits 0 to 3.
The other bits are not implemented. (‘0’ at reading).