7480 Group and 7481 Group User's Manual
1-137
HARDWARE
Stopping Transmission/Reception of UART
In order to stop the transmit operation of UART, clear the transmit enable bit of the serial I/O
control register to ‘0’. As a result, the following stop and initialization of transmit operation are
performed:
To stop and initialize the clock supplied to the transmit shift register
To clear the transmit shift register.
To clear the transmit buffer empty flag and transmit shift completion flag
In order to stop the receive operation of UART, clear the receive enable bit or the serial I/O enable
bit of the serial I/O control register to ‘0’. As a result, the following stop and initialization of the
receive operation are performed:
To stop and initialize the clock supplied to the receive shift register
To clear the receive shift register
To clear every error flag
To clear the receive buffer full flag
Re-setting Serial I/O Control Register
Re-set the serial I/O control register according to the following sequence to stop and initialize transmit
and receive operations:
Clear both of the transmit and receive enable bits of the serial I/O control register to ‘0’.
Set bits 0 to 3 and 6 of the serial I/O control register.
Set both the transmit and receive enable bits to ‘1’.
(Procedures and can be performed simultaneously with the LDM instruction.)
Using Serial I/O Transmit Interrupt and Serial I/O Receive Interrupt
Set the associated registers in the following sequence to use serial I/O transmit interrupt.
Clear the serial I/O transmit interrupt enable bit of interrupt control register 1 to ‘0’.
Set the serial I/O control register.
Execute one or more instructions such as NOP.
Clear the serial I/O transmit interrupt request bit of interrupt request register 1 to ‘0’.
Set the serial I/O transmit interrupt enable bit of interrupt control register 1 to ‘1’.
REASONS 1: If normal port pins are switched to serial I/O pins with the serial I/O control register,
the serial I/O transmit interrupt request bit may become ‘1’.
2: If the transmit enable bit of the serial I/O control register is set to ‘1’, the transmit
buffer empty flag and the transmit shift completion flag are ‘1’. As a result, the serial
I/O transmit interrupt request bit becomes ‘1’ regardless of the state of the transmit
interrupt source selection bit of the serial I/O control register, and the interrupt
request is generated.
Set the associated registers in the following sequence to use serial I/O receive interrupt.
Clear the serial I/O receive interrupt enable bit of interrupt control register 1 to ‘0’.
Set the serial I/O control register.
Execute one or more instructions, such as NOP.
Clear the serial I/O receive interrupt request bit of interrupt request register 1 to ‘0’.
Set the serial I/O receive interrupt enable bit of interrupt control register 1 to ‘1’.
REASON: If normal port pins are switched to serial I/O pins with the serial I/O control register, the
serial I/O receive interrupt request bit may become ‘1’.
1.14 Serial I/O