參數(shù)資料
型號(hào)： M37516M8-XXXHP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁(yè)數(shù)： 20/90頁(yè)
文件大?。?/td> 1299K
代理商： M37516M8-XXXHP
27
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7516 Group
Fig. 24 Block diagram of Serial I/O2
Fig. 25 Timing chart of Serial I/O2
D7
D0
D1
D2
D3
D4
D5
D6
Transfer clock (Note 1)
Serial I/O2 output SOUT2
Serial I/O2 input SIN2
Receive enable signal SRDY2
Write-in signal to
serial I/O2 register
(Note 2)
Serial I/O2 interrupt request bit set
.
1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected
by setting bits 0 to 2 of serial I/O2 control register 1.
2: When the internal clock is selected as a transfer clock, the SOUT2 pin has high impedance after transfer completion.
Notes
XIN
“1”
“0”
“1”
“0”
“1”
SRDY2
S
C
L
K
2
“0”
“1”
1/8
1/16
1/32
1/64
1/128
1/256
“1”
“0”
XCIN
“10”
“00”
“01”
Data bus
Serial I/O2
interrupt request
Serial I/O2 port selection bit
Serial I/O counter 2 (3)
Serial I/O2 register (8)
Synchronous circuit
Serial I/O2 port selection bit
Serial I/O2 synchronous
clock selection bit
SRDY2 output enable bit
External clock
Internal synchronous
clock selection bits
D
iv
id
e
r
Optional transfer bits (3)
P02/SCLK2
P01/SOUT2
P00/SIN2
P02 latch
P01 latch
P03 latch
P03/SRDY2
P43/SCMP2/INT2
Serial I/O2 I/O comparison
signal control bit
P43 latch
Q
D
Main clock division ratio
selection bits (Note)
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.
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