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| 型號： | M37534E4FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 32/55頁 |
| 文件大?。?/td> | 610K |
| 代理商： | M37534E4FP |
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7534 Group
Rev.2.00 Jun 21, 2004 page 32 of 54
REJ03B0099-0200Z
A/D Converter
The functional blocks of the A/D converter are described below.
[A/D conversion register] AD
The A/D conversion register is a read-only register that stores the
result of A/D conversion. Do not read out this register during an A/D
conversion.
[A/D control register] ADCON
The A/D control register controls the A/D converter. Bit 2 to 0 are
analog input pin selection bits. Bit 4 is the AD conversion completion
bit. The value of this bit remains at “0” during A/D conversion, and
changes to “1” at completion of A/D conversion.
A/D conversion is started by setting this bit to “0”.
[Comparison voltage generator]
The comparison voltage generator divides the voltage between V
SS
and V
REF
by 1024 by a resistor ladder, and outputs the divided volt-
ages. Since the generator is disconnected from V
REF
pin and V
SS
pin, current is not flowing into the resistor ladder.
[Channel Selector]
The channel selector selects one of ports P2
7
/AN
7
to P2
0
/AN
0,
and
inputs the voltage to the comparator.
[Comparator and control circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores its result into the A/D
conversion register. When A/D conversion is completed, the control
circuit sets the AD conversion completion bit and the AD interrupt
request bit to “1”. Because the comparator is constructed linked to a
capacitor, set f(X
IN
) to 500 kHz or more during A/D conversion.
Fig. 35 Structure of A/D control register
Fig. 36 Structure of A/D conversion register
Fig. 37 Block diagram of A/D converter
A
(
/
A
D
D
n
C
c
o
O
n
N
t
r
o
:
l
a
r
d
e
g
d
i
s
e
t
s
e
s
r
r
0
0
3
4
1
6
)
N
A
o
D
t
0
1
c
u
s
o
:
:
e
n
C
C
d
v
o
o
(
r
v
v
r
s
e
e
e
i
t
o
r
r
u
n
s
s
r
i
o
i
o
n
c
s
o
n
n
m
i
n
c
“
0
”
l
w
e
r
o
p
h
t
i
g
l
e
n
r
e
t
n
b
s
d
r
e
i
t
s
a
d
)
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
e
n
n
p
p
o
m
o
e
e
b
7
b
0
A
a
0
0
1
1
0
0
1
1
l
o
0
1
0
1
0
1
0
1
g
:
:
:
:
:
:
:
:
i
P
P
P
P
P
P
P
P
n
p
2
0
/
2
1
/
2
2
/
2
3
/
2
4
/
2
5
/
2
6
/
2
7
/
u
t
A
A
A
A
A
A
A
A
p
N
0
N
1
N
2
N
3
N
4
N
5
N
6
N
7
i
n
s
e
l
e
c
t
i
o
n
b
i
t
s
0
0
0
0
1
1
1
1
Read 8-bit (Read only address 0035
16
)
b7
b0
b9
b8
b7
b6
b5
b4
b3
b2
(Address 0035
16
)
Read 10-bit (read in order address 0036
16
, 0035
16
)
b7
b0
b9
b8
(Address 0036
16
)
b7
b0
b7
b6
b5
b4
b3
b2
b1
b0
(Address 0035
16
)
High-order 6-bit of address 0036
16
returns “0” when read.
A
/
D
(
A
c
d
o
d
n
r
t
r
s
o
s
l
r
0
e
0
g
3
i
s
4
1
t
e
6
)
r
e
C
h
a
n
n
e
l
s
e
l
e
c
t
o
r
A/D control circuit
R
e
s
i
s
t
o
r
l
a
d
d
e
r
V
S
S
Comparator
A
/
D
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b7
b0
D
a
t
a
b
u
s
3
1
0
P
P
P
P2
3
/AN
3
P
P
P
P
2
0
/
2
1
/
2
2
/
A
A
A
N
0
N
1
N
2
2
4
/
2
5
/
2
6
/
2
7
/
A
A
A
A
N
4
N
5
N
6
N
7
A/D conversion register (low-order)
(
(
A
d
d
r
e
s
s
0
0
3
6
1
6
)
A
d
d
r
e
s
s
0
0
3
5
1
6
)
A
/
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
h
i
g
h
-
o
r
d
e
r
)
V
R
E
F
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